JPH0736441B2 - Method for manufacturing vertical field effect transistor - Google Patents
Method for manufacturing vertical field effect transistorInfo
- Publication number
- JPH0736441B2 JPH0736441B2 JP61135295A JP13529586A JPH0736441B2 JP H0736441 B2 JPH0736441 B2 JP H0736441B2 JP 61135295 A JP61135295 A JP 61135295A JP 13529586 A JP13529586 A JP 13529586A JP H0736441 B2 JPH0736441 B2 JP H0736441B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- polysilicon
- mask
- conductivity type
- thick portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、縦型電界効果トランジスタ（以下、縦型MOSF
ETと記す。）の製造方法に関し、特に工程の簡略化、製
品の特性安定化及び素子の縮小化に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical field effect transistor (hereinafter referred to as vertical MOSF).
It is written as ET. ), Particularly, to the simplification of the process, the stabilization of the characteristics of the product, and the reduction of the size of the device.
従来の縦型電界効果トランジスタは、第３図に示すよう
な製造方法で製造されていた。まず第３図（ａ）に示す
ように、半導体基板１上に酸化膜２を成長し、フォトリ
ソグラフィ技術を用いて、第３図（ｂ）に示すようにレ
ジスト10を形成し、酸化膜２をエッチングしてP-ベース
領域11を形成する（第３図（ｃ））。さらに第３図
（ｄ）に示すように、酸化膜形成後P-ベース領域11上に
酸化膜12を残し、第３図（ｅ）に示すようにポリシリコ
ンを成長し、フォト・リソグラフィ技術を用いて、ポリ
シリコン３を形成し、ポリシリコン３とマスク酸化膜12
をマスクにして、イオン注入10〜100keV程度のイオン注
入により（不純物ピーク深を、500〜3000Å）Ｐベース
領域５及び、N+ソース領域６を形成し、さらに第３図
（ｆ）に示すように層間絶縁膜７を形成し、フォト・リ
ソグラフィ技術を用いて窓あけを行ない、ソースアルミ
電極８を形成する。The conventional vertical field effect transistor is manufactured by the manufacturing method as shown in FIG. First, as shown in FIG. 3 (a), an oxide film 2 is grown on a semiconductor substrate 1, and a resist 10 is formed as shown in FIG. 3 (b) using a photolithography technique. Is etched to form a P - base region 11 (FIG. 3 (c)). Further, as shown in FIG. 3 (d), after the oxide film is formed, the oxide film 12 is left on the P − base region 11 and polysilicon is grown as shown in FIG. 3 (e). Polysilicon 3 is formed using the polysilicon 3 and the mask oxide film 12
Is used as a mask to form a P base region 5 and an N + source region 6 by ion implantation of 10 to 100 keV (impurity peak depth is 500 to 3000 Å), and as shown in FIG. 3 (f). An inter-layer insulating film 7 is formed on the substrate, a window is formed by using a photolithography technique, and a source aluminum electrode 8 is formed.
上述した従来の縦型電界効果トランジスタの製造方法に
おいては、ポリシリコンをマスクにして、低エネルキィ
オン注入を用いてベース領域を形成していたので、不純
物ピーク深さが、500〜3000Åとなりバック・ゲート部
には、先にベース領域と同じ導電型の不純物領域を形成
しておかなければベース領域がつながらず、耐圧が小さ
くなり、また、ベース領域間に不純物領域を形成する場
合、工程が多くなるという欠点を持っていた。In the above-described conventional method for manufacturing a vertical field effect transistor, the base region is formed by using low energy implantation using polysilicon as a mask, so that the impurity peak depth is 500 to 3000 Å and the back gate is formed. If the impurity region of the same conductivity type as that of the base region is not formed in the first portion, the base region will not be connected and the withstand voltage will be low, and if the impurity region is formed between the base regions, the number of steps will increase. Had the drawback.
また、Ｐベース間にすき間が発生するので、P-ベース領
域が必要なため、工程が複雑になりさらに、P-ベースと
Ｐベースを別々に形成するため、目ずれなどが発生した
場合、チャンネル部などが重なり、特性が安定しないと
いう欠点を持っていた。In addition, since a gap is generated between the P bases, the P - base region is required, which complicates the process. Further, since the P - base and the P-base are formed separately, when a misalignment occurs, the channel It had the drawback that the characteristics were not stable due to overlapping parts.
本発明は、縦型MOSFETの製造方法において、ポリシリを
マスクにして、Ｐベース領域を超高エネルギ・イオンを
用いて（例えば、0.1〜5MeV）酸化膜を通して形成し、
逆に、N+ソース領域は、ポリシリ及び酸化膜をマスクと
して形成する。The present invention relates to a method of manufacturing a vertical MOSFET in which a P base region is formed through an oxide film using ultra-high energy ions (for example, 0.1 to 5 MeV) by using polysilicon as a mask,
On the contrary, the N + source region is formed by using the polysilicon and the oxide film as a mask.
本発明の縦型電界効果トランジスタの製造方法は、半導
体基板表面にソース及びゲートを有し裏面にドレインを
有する縦型電界効果トランジスタの製造方法において、
半導体基板表面に酸化膜を厚さに段差をつけて成長する
工程と、その上にポリシリコンを成長する工程と、フォ
トリングラフィ技術を用いて酸化膜厚の厚い部分を中心
にポリシリコンをエッチングする工程と、エッチング用
マスクおよび残存ポリシリコンをマスクにして超高エネ
ルギーイオン注入を行い半導体基板と逆の導電型の第１
不純物領域を形成する工程と、さらにその第１不純物領
域内に前記残存ポリシリコン及び前記酸化膜厚の厚い部
分をマスクにして半導体基板と同じ導電型の第２不純物
領域を形成する工程とを有することを特徴とする。A method for manufacturing a vertical field effect transistor according to the present invention is a method for manufacturing a vertical field effect transistor having a source and a gate on a semiconductor substrate surface and a drain on a back surface,
A step of growing an oxide film on the surface of a semiconductor substrate with a step difference in thickness, a step of growing polysilicon on the oxide film, and a step of etching polysilicon with a thick oxide film centered by photolinography technology. And a high-energy ion implantation using a mask for etching and the remaining polysilicon as a mask, which has a conductivity type opposite to that of the semiconductor substrate.
And a step of forming an impurity region and a step of forming a second impurity region of the same conductivity type as that of the semiconductor substrate in the first impurity region by using the remaining polysilicon and the thick oxide film portion as a mask. It is characterized by
第１図は、本発明の第１実施例の断面図である。 FIG. 1 is a sectional view of the first embodiment of the present invention.
第１図（ａ）に示すように、半導体基板１に、酸化膜２
を段差例えば、3000Å〜２μｍをつけて成長させ、その
上に第１図（ｂ）に示すようにポリシリコン３を成長
し、フォト・リソグラフィ技術を用いてエッチングし、
その上より、超高エネルギーイオン注入４（例えば0.1
〜5MkeV）を行ない、イオン注入後のピーク値が、5000
Å〜３μｍになるようにする。次にポリシリコン３及び
レジスト15をマスクにして、酸化膜２を通してＰベース
領域５を形成する（第１図（ｃ））。次に、ポリシリ３
及び、酸化膜２をマスクにして、N+ソース領域６を形成
する（第１図（ｄ））。As shown in FIG. 1A, the oxide film 2 is formed on the semiconductor substrate 1.
Is grown with a step, for example, 3000 Å to 2 μm, on which polysilicon 3 is grown as shown in FIG. 1 (b) and is etched by using photolithography technology.
From above, ultra high energy ion implantation 4 (eg 0.1
~ 5MkeV), the peak value after ion implantation is 5000
Å ~ 3μm. Next, using the polysilicon 3 and the resist 15 as a mask, the P base region 5 is formed through the oxide film 2 (FIG. 1 (c)). Next, police
Then, the N + source region 6 is formed using the oxide film 2 as a mask (FIG. 1 (d)).
以上のようにすることにより、P-領域を形成することな
く、バッグゲート部14を形成できるため、工程を簡略化
できる。また、P-ベースの大きさをセル設計時に考慮に
入れる必要がなくなるため、セルの縮小化を計ることが
できる。By doing so, the bag gate portion 14 can be formed without forming the P − region, so that the process can be simplified. Moreover, since it is not necessary to take the size of the P - base into consideration when designing the cell, the cell can be downsized.
第２図は、本発明の第２の実施例の縦断面図である。第
２図は、第１図のレジスト15を、アルミカバー16に変更
した例であり、他は第１の実施例と同一である。FIG. 2 is a vertical sectional view of the second embodiment of the present invention. FIG. 2 shows an example in which the resist 15 in FIG. 1 is replaced with an aluminum cover 16, and the other parts are the same as those in the first embodiment.
以上説明したように本発明は、縦型MOSFETの製造におい
て、超高エネルギーイオン注入を用いることにより、Ｐ
ベース領域は、ポリシリゲートもしくは、ポリシリ・エ
ッチング時のカバーをマスクにして、バッグ・ゲート部
酸化膜を通して形成し、N+ソース領域は、ポリシリコン
及び酸化膜をマスクにして形成する。As described above, according to the present invention, in the manufacture of the vertical MOSFET, by using the ultra high energy ion implantation, the P
The base region is formed through the bag / gate portion oxide film using the polysilicon gate or the cover during the polysilicon etching as a mask, and the N + source region is formed using the polysilicon and the oxide film as a mask.
これにより、P-ベース領域を形成しなくてよいので、工
程を簡略化でき、また、バック・ゲート面積を確保すれ
ば、P-層の拡散拡がりなどを考慮に入れることなく素子
を設計することができるため、それだけ素子の縮小化を
計ることができるという効果がある。As a result, the P - base region does not have to be formed, so the process can be simplified, and if the back gate area is secured, the device can be designed without considering the diffusion spread of the P - layer. Therefore, there is an effect that the device can be downsized accordingly.
第１図（ａ）〜（ｄ）は本発明の第１の実施例の工程断
面図、第２図（ａ）〜（ｄ）は本発明の第２の実施例の
工程断面図、第３図（ａ）〜（ｆ）は従来の縦型MOSFET
の工程断面図である。 １……Ｎ型半導体基板、２……酸化膜、３……ポリシ
リ、４……超高エネルギイオン注入、５……Ｐベース領
域、６……N+ソース領域、７……層間絶縁膜、８……ソ
ース・アルミ電極、９……ドレイン電極、10……フォト
・レジスト、11……P-ベース領域、12……マスク酸化
膜、13……チャンネル部、14……バック・ゲート部、15
……レジスト、16……アルミ・カバー。1 (a) to (d) are process cross-sectional views of the first embodiment of the present invention, and FIGS. 2 (a) to (d) are process cross-sectional views of the second embodiment of the present invention. Figures (a) to (f) are conventional vertical MOSFETs.
FIG. 1 ... N-type semiconductor substrate, 2 ... oxide film, 3 ... polysilicon, 4 ... ultra high energy ion implantation, 5 ... P base region, 6 ... N + source region, 7 ... interlayer insulating film, 8 ... Source aluminum electrode, 9 ... Drain electrode, 10 ... Photo resist, 11 ... P - base region, 12 ... Mask oxide film, 13 ... Channel part, 14 ... Back gate part, 15
…… Resist, 16 …… Aluminum cover.
Claims (1)
る酸化膜を形成する工程と、前記酸化膜上にポリシリコ
ンを成長する工程と、前記厚い部分を中心に含む所定の
領域の前記ポリシリコンを選択的にエッチングし除去す
る工程と、前記エッチングに用いたマスクと残存ポリシ
リコンをマスクとして、前記厚い部分を通すエネルギー
でイオン注入を行い、前記厚い部分を含む前記酸化膜下
の前記一導電型半導体基板中に逆導電型不純物を導入し
逆導電型ベース領域を形成する工程と、前記残存ポリシ
リコンと前記酸化膜の前記厚い部分をマスクとして一導
電型不純物を導入し前記逆導電型ベース領域内に一導電
型ソース領域を形成する工程とを有することを特徴とす
る縦型電界効果トランジスタの製造方法。1. A step of forming an oxide film having a thick portion on a surface of a one-conductivity-type semiconductor substrate, a step of growing polysilicon on the oxide film, and a step of forming a polysilicon film in a predetermined region including the thick portion as a center. Selectively etching and removing silicon, and using the mask used for the etching and the residual polysilicon as a mask, ion implantation is performed with energy passing through the thick portion, and the ion implantation under the oxide film including the thick portion is performed. A step of introducing an opposite conductivity type impurity into a conductivity type semiconductor substrate to form an opposite conductivity type base region; and introducing an impurity of one conductivity type by using the remaining polysilicon and the thick portion of the oxide film as a mask. A step of forming a source region of one conductivity type in the base region, a method of manufacturing a vertical field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135295A JPH0736441B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135295A JPH0736441B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291066A JPS62291066A (en) | 1987-12-17 |
| JPH0736441B2 true JPH0736441B2 (en) | 1995-04-19 |
Family
ID=15148358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135295A Expired - Fee Related JPH0736441B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736441B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187117A (en) * | 1991-03-04 | 1993-02-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
| CN102484073B (en) * | 2009-07-31 | 2015-07-22 | 富士电机株式会社 | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61158180A (en) * | 1984-12-28 | 1986-07-17 | Tdk Corp | Manufacture of mis-type semiconductor device |
-
1986
- 1986-06-10 JP JP61135295A patent/JPH0736441B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62291066A (en) | 1987-12-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |