JPS63102264A - Thin film semiconductor device - Google Patents

Abstract

PURPOSE:To stabilize a channel forming region thereby to be able to laminate regions in a thin film semiconductor device by elevationally interposing the channel forming region of a thin film semiconductor region between gate electrodes. CONSTITUTION:A second gate electrode 22 which becomes a lower gate electrode of a first thin film semiconductor region 25 is selectively formed on a semiconductor substrate 21, and a third gate insulating film 24 is formed on the surface. A first thin film semiconductor region 25, a first gate insulating film 26, a first gate electrode 27, a second gate insulating film 28, a second thin film semiconductor layer 29, a fourth gate insulating film 30, and a third gate electrode 31 are sequentially formed thereon. The channel forming regions 34 and 37 of first and second MOS transistors 43 and 44 are elevationally interposed between upper and lower gate electrodes 27 and 22, 31 and 27, respectively. Thus, with one gate electrode as a stationary electrode the potential of the channel forming region is stabilized, and the other gate electrode can be used as a signal input electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a technique for improving the degree of integration of thin film semiconductor devices.

[Prior art]

FIG. 7 is a cross-sectional view of an example of a conventional thin film semiconductor device (for example, IEEE Transactions on Electron Devices IEEE TRAN).
SACTIONS ON ELECTRON DEVI
C.E.S.

Vol ED-32, No. 2 p258-281 (Mt).

In the device shown in FIG. 7, a thin film semiconductor region 2 is formed on an insulating substrate 1, and a source region 5, a drain region 6, and a channel forming region 7 are provided within the thin film semiconductor region 2. A gate electrode 4 is provided on the channel forming region 7 with a gate insulating film 3 interposed therebetween.

Further, 8 is a source electrode, 9 is a drain electrode, and IO is an interlayer insulating film.

Although the conventional example in FIG. 7 shows an example in which a polysilicon thin film is used as the thin film semiconductor region, other materials such as a single crystal thin film recrystallized by laser annealing, an amorphous silicon thin film, etc. may also be used. I can do it.

[Problem that the invention seeks to solve]

In the conventional thin film semiconductor device as described above, since the channel forming region 7 is in a potential floating state, the potential corresponding to the substrate potential of a normal MOSFET is not stable, and moreover, the structure shown in FIG. If you try to improve the degree of integration by simply stacking transistors, the potential of the upper and lower transistors will interfere, making the potential of the channel formation region even more unstable, which will adversely affect transistor characteristics, such as malfunction. was there.

The present invention has been made in order to solve the problems of the prior art as described above, and aims to provide a thin film semiconductor device that stabilizes the potential of a channel forming region and enables stacking. be.

[Means to solve the problem]

In order to achieve the above object, in the present invention, the potential of the channel forming region of the thin film semiconductor region is stabilized by sandwiching the upper and lower sides of the channel forming region between gate electrodes.

This will be explained in detail below.

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 110 is a first thin film semiconductor region, which includes a source region 111, a channel forming region 1
12. A drain region 113 is formed.

Also, in the second thin film semiconductor region 120, a source region 121, a channel forming region 122, a drain region 12
3 is formed.

These two thin film semiconductor regions 110 and 120 are stacked on each other with a gate insulating film interposed therebetween.

Furthermore, between the two thin film semiconductor regions and on the outside of each, a first gate electrode 105, a second gate electrode 106, and a third gate electrode 107 are formed with gate insulating films interposed therebetween. .

Therefore, the channel forming region 112 of the first thin film semiconductor region 110 is sandwiched between the first gate electrode 105 and the second gate electrode 106, and the second thin film semiconductor region 12
0 channel formation region 122 is the first gate electrode 105
and the third gate electrode 107.

Then, the first thin film semiconductor region 110, the first gate electrode 105. The second gate electrode 106, the first gate insulating film 101, and the third gate insulating film 103 constitute a first MOS transistor, and the second thin film semiconductor region 120, the first gate electrode 105, The third gate electrode 107, the second gate insulating film 102, and the fourth gate insulating film 104 constitute a second MOS transistor.

Note that in FIG. 1, a part of the gate insulating film provided between the first thin film semiconductor region 110 and the second thin film semiconductor region 120 can be omitted if necessary (for example, , when two stacked transistors are connected in series or in parallel, as shown in the embodiments of FIGS. 3 and 4 described later).

[Effect]

As described above, in the configuration of FIG. 1, the channel forming regions 112 and 122 of the first MOS transistor and the second MOS transistor are formed by the upper and lower two gate electrodes 105 and 106 and 105 and 107, respectively. Because of the sandwiched structure, it is possible to use one of the gate electrodes as a fixed electrode to stabilize the potential of the channel formation region, and the other gate electrode as a signal input electrode. 2 upper and lower MO
It is possible to operate the S transistor independently without being influenced by other transistors.

For example, by fixing the first gate electrode 105 to GND (the source potential of each MOS transistor), the two transistors can be operated independently of each other.

[Embodiments of the invention]

FIG. 2 is a cross-sectional view of an embodiment of the present invention, in which (A) shows a case where the thin film semiconductor device of the invention is formed on a semiconductor substrate 21, and (B) shows a case where the thin film semiconductor device of the invention is formed on an insulating substrate 1. A case where a thin film semiconductor device is formed is illustrated.

First, in case (A), a first layer is formed on the surface of the semiconductor substrate 21.
A second gate electrode 22 that becomes the lower gate electrode of the thin film semiconductor region 25 is selectively formed, a third gate insulating film z4 is formed on the surface of the second gate electrode 22, and the first thin film semiconductor region 25, First gate insulating film 26, first gate electrode 27, second gate insulating film 28, second thin film semiconductor region 29. Fourth gate insulating film 30, third gate electrode 31
form.

Further, in the first thin film semiconductor region 25, a high concentration diffusion region 32 (source region), a high concentration diffusion region 33 (drain region), and a channel forming region 34 are formed, and these and the first gate electrode 27 and second gate electrode 22
and constitute a first MOS transistor 43.

Further, a high concentration diffusion region 35 (source region), a high concentration diffusion region 36 (drain region), and a channel forming region 37 are formed also in the second i-adult conductor region 29, and these and the first gate The electrode 27 and the third gate electrode 31 constitute a second MOS transistor 44 .

In the configuration of FIG. 2(A) as described above, the first M
OS transistor 43 and second MOS transistor 4
Since the channel formation region 33.37 of No. 4 is sandwiched between two upper and lower gate electrodes 27.22 and 31.27, the potential of the channel formation region is stabilized by using one of the gate electrodes as a fixed electrode. It is possible to use the other gate electrode as a signal input electrode, thereby allowing the two MOS transistors 43 and 44 stacked one above the other to operate independently without being influenced by other transistors. is possible. for example,
By fixing the potential of the first gate electrode 27 to GND, it is possible to operate independently.

The structure shown in FIG. 2(B) is a case where the thin film semiconductor device of the present invention is formed on the insulating substrate 1, and the other parts are the same as in FIG. 2(A).

Further, in FIG. 2, the structure of the electrodes for connecting the first to third gate electrodes to the outside is not shown.

Next, FIGS. 3 to 5 show other embodiments of the present invention, in which (A) is a sectional view and (B) is an equivalent circuit diagram.

First, FIG. 3 shows a case where two Mo3) transistors 43 and 44 are connected in parallel.

In FIG. 3, an input voltage is applied to the second gate electrode 22 of the first MOS transistor 43, and the second MOS transistor 43
In the S transistor 44, an input voltage is applied to the third gate electrode 31.

The respective sources and drains are directly laminated without intervening an insulating film, and have a source electrode 50 and a drain electrode 5, respectively.
1 to the outside.

Further, in this case, the first gate electrode 27 is formed as a back gate of the first and second MOS transistors 43 and 44, and the first gate electrode 27 forms a channel of the first MOS transistor 43. Formation area 3
4 and the channel forming region 37 of the second MOS transistor 44 are each shielded to prevent mutual interference.

Next, the embodiment of FIG. 4 has two MOS transistors 4
3 and 44 are connected in series.

In FIG. 4, in the first MOS transistor 43,
An input voltage is applied to the second gate electrode 22, and the second M
In the OS transistor 44, an input voltage is applied to the third gate electrode 31.

Further, the drain 53 of the first MoS transistor 43 and the source 35 of the second MOS transistor 44 are directly connected.

Note that, as in the case of FIG. 3, the first gate electrode 2
7 is formed as the back gate of the first and second MoS transistors 43 and 44, and the two stacked transistors do not interfere with each other.

Next, in the embodiment of FIG. 5, two MOS transistors 4
3 and 44 are connected in series to form a CMOS inverter.

In FIG. 5, the first MOS transistor 43 is
The channel MOS transistor, the second MOS transistor 44, is a P-channel MOS transistor.

Then, an input voltage is applied to the first gate electrode 27 serving as a common gate of these rain transistors.

Further, the second gate electrode 22 is used as a back gate of the first Mo8)-transistor 43.
The same voltage as the source voltage of the OS transistor is applied.

Further, the third gate electrode 31 is used as a back gate of the second Mo3)-transistor 44, and is usually used as a back gate of the second Mo3)-transistor 44.
The same voltage as the source voltage of the OS transistor 44 is applied.

Next, FIG. 6 is a manufacturing process diagram of the embodiment shown in FIG. 2(A).

First, in (A), a field oxide film 23 is formed on the surface of a semiconductor substrate 21, and a third gate insulating film 24 is formed on a part of the field oxide film 23. Thereafter, impurities are introduced by ion implantation to form the second gate electrode 22. 6th
The example in the figure shows an example in which a gate electrode of an n diffusion layer is provided on a p-type substrate, but a p+ diffusion layer is provided on an n-type substrate, or an n+ diffusion layer is formed on the surface of a p-well formed in an n-type substrate. The gate electrode can also be formed by a layer or the like.

Next, in (B), the surface is coated with 0.0% by CVD method or the like.
A Si thin film having a thickness of about 1 to 1 - is formed and is used as the first thin film semiconductor region 25 . This Si thin film may be an amorphous Si film, a polysilicon film, a laser annealed Si recrystallized film, or the like. Thereafter, the first gate insulating film 26 is formed by a thermal diffusion method, a CVD method, or the like.
form.

Next, in (C), a MOS transistor structure is formed by a normal process. Here, a case will be described in which a self-alignment method is used in which the source and drain are formed using the gate electrode as a mask.

First, impurities are introduced throughout the first thin film semiconductor region 25 in order to determine the threshold voltage and the like of the transistor. Note that this step may be performed at any time after forming the first thin film semiconductor region and before forming the first gate electrode 27.

Next, a gate electrode is formed on the entire surface of the first gate insulating film 26, and photoetching is performed to leave only a portion corresponding to the second gate electrode 22, thereby forming a first gate electrode 27. do. Note that polysilicon, high melting point metal, silicide, etc. are used as the material for the gate electrode.

Next, using the first gate electrode 27 as a mask, high concentration impurities are selectively implanted into the first thin film semiconductor region 25 by ion implantation or the like. As a result, highly doped diffusion regions 32, 33 and channel formation region 34, which become the source and drain of the MOS transistor, are formed. Thereafter, the second gate insulating film 28 is formed by a thermal diffusion method, a CVD method, or the like.
form.

Next, in (D), the surface is again coated with 0.1
A Si thin film having a thickness of about 1-1 is formed, and this is used as the second thin film semiconductor region 29. Note that this Si thin film 29 can also be formed of single crystal polysilicon, amorphous silicon, etc. on the Si@ film 2 film 5 described in Makoto. Thereafter, a fourth gate insulating film 30 is formed using a thermal oxidation method, a CVD method, or the like.

Next, in (E), high concentration diffusion regions 35 and 36 and channel formation regions 37 which will become the source and drain of the second MOS transistor are formed.

Next, in (F), an interlayer insulating film 42 such as PSG or Si3N is formed on the entire surface by CVD method or the like, and after removing the insulating film at a predetermined portion, electrodes and wiring are formed using a metal such as M. . In addition, in (F), the first
The source electrode 38 and drain electrode 39 of the MOS transistor 43 and the source electrode 40 and drain electrode 41 of the second MOS transistor 44 are illustrated.

〔Effect of the invention〕

As explained above, in the present invention, since the stacked thin film semiconductor regions are configured to be sandwiched between gate electrodes, it is possible to prevent adverse effects on transistor characteristics due to mutual interference of transistors in the stacked structure. This provides an excellent effect of improving the degree of integration.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Figs. 2 to 5 are illustrations of embodiments of the present invention, Fig. 6 is a manufacturing process diagram of the device shown in Fig. 2, and Fig. 7 is an example of the conventional device. FIG. Explanation of symbols> 101...First gate insulating film 102...Second gate insulating film 103...Third gate insulating film 104...Fourth gate insulating film 105...Th 1 gate electrode 106...2nd gate electrode 107...3rd gate electrode 110...1st thin film semiconductor region 120...2nd thin film semiconductor region 111.121...source region 112.122...Channel formation region 113.123
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Claims (1)

[Claims] The first thin film semiconductor region has a first
A first gate electrode is provided through a gate insulating film, a second thin film semiconductor region is laminated thereon through a second gate insulating film, and a main surface opposite to the first thin film semiconductor region is formed. A second gate electrode is disposed at a position corresponding to the first gate electrode above through a third gate insulating film, and further on a side of the second thin film semiconductor region opposite to the first thin film semiconductor region. A thin film semiconductor device characterized in that a third gate electrode is disposed on the main surface at a position corresponding to the first gate electrode with a fourth gate insulating film interposed therebetween.