JPS5850752A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5850752A JPS5850752A JP14775181A JP14775181A JPS5850752A JP S5850752 A JPS5850752 A JP S5850752A JP 14775181 A JP14775181 A JP 14775181A JP 14775181 A JP14775181 A JP 14775181A JP S5850752 A JPS5850752 A JP S5850752A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- layer
- semiconductor substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 25
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 17
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 238000000926 separation method Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、半導体装置よ如詳細に述べるならば、ＶＩＰ
（Ｖ−ｇｒｏｏｖｅ ｌ５ｏｌａｔ１ｏｎ Ｐｏ
１ｙａｒｙｓｔａｌｂａｃｋｆｌｌｌ ）絶縁層分離構
造を利用して半導体基板アースをとった半導体装置の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION If the present invention is described in detail as a semiconductor device,
(V-groove l5olat1on Po
This invention relates to a method of manufacturing a semiconductor device in which a semiconductor substrate is grounded using an insulating layer separation structure.
半導体基板（シリコンウェハ）上にエピタキシャル成長
層を形成し、このエピタキシャル成長層内にトランジス
タなどの能動素子および抵抗などの受動素子を形成する
際にはこれら素子をアイソレージ、ン（分離）する必要
があシ、また適切な位置にて基板にアースをとるための
導体部分をエピタキシャル成長層に設ける必要がある。When an epitaxial growth layer is formed on a semiconductor substrate (silicon wafer) and active elements such as transistors and passive elements such as resistors are formed within this epitaxial growth layer, it is necessary to isolate these elements. Furthermore, it is necessary to provide a conductor portion in the epitaxial growth layer for grounding the substrate at an appropriate position.
アイソレージ、ンをＰＮ接合分離方式で行なうならば、
基板まで達する不純物拡散領域を分離層と同時にアース
をとるための導体部分とすることができる。If isolation is performed using the PN junction separation method,
The impurity diffusion region reaching the substrate can be used as a conductor portion for grounding at the same time as the separation layer.
半導体基板がＰ型であればＮ型のエピタキシャル成長層
にＰ型不純物（例えばがロン）を分離拡散するわけであ
るが、この分離拡散にはかなシの高温で長時間の熱処理
を施ζす必要がある。例えば、２．４μｍ厚さのエピタ
キシャル成長層にＩロン（Ｂ）を基板に達するまで拡散
するには１１５０ （Ｃ）で４０分かかる。この熱処理
のために半導体装置に形成される埋込層（ｂｕｒ量・ｄ
ｌａｙ＠ｒ 、例えばＮ＋埋設領域）からＮｉｌ不純
物も拡散して埋込層が工ビタキシャル層内へ拡大し、ま
た、結晶欠陥が鱒起される。これらのために半導体装置
の特性が劣化する。If the semiconductor substrate is P-type, P-type impurities (for example, Ron) are separated and diffused into the N-type epitaxial growth layer, but this separation and diffusion requires heat treatment at extremely high temperatures for a long time. There is. For example, it takes 40 minutes at 1150 (C) to diffuse Iron (B) into a 2.4 μm thick epitaxially grown layer until it reaches the substrate. A buried layer (bur amount/d
Nil impurities also diffuse from the lay@r (for example, the N+ buried region), the buried layer expands into the micro-bitaxial layer, and crystal defects are generated. These deteriorate the characteristics of the semiconductor device.
ｖＩｐｇ造の絶縁層分離を利用した半導体装置では、第
１図から明らかなように二酸化シリコン（ｓｉｏ２）膜
の絶縁膜のために基板とアースをとるのにＶＩＰ構造は
使えない。なお、第１図は半導体装置のＶＩＰ構造部分
の概略断面図であって、半導体基板１とその上のエピタ
キシャル成長層２に形成されたＶ溝３がＶ溝表面上の酸
化ＩＩ（８１０ｚ膜）４および多結晶（４す）シリコン
層５によって満たされ、そして多結晶シリコン層５の表
面上に厚い酸化膜（Ｓｉｏ２ ｊｌｌ） ６ カある。As is clear from FIG. 1, in a semiconductor device using insulating layer separation using the vIpg structure, the VIP structure cannot be used to connect the substrate to the ground because of the silicon dioxide (SIO2) insulating film. Note that FIG. 1 is a schematic cross-sectional view of a VIP structure portion of a semiconductor device, in which a V-groove 3 formed in a semiconductor substrate 1 and an epitaxially grown layer 2 thereon is formed by an oxide II (810z film) 4 on the surface of the V-groove. and a polycrystalline silicon layer 5, and there is a thick oxide film (Sio2jll) 6 on the surface of the polycrystalline silicon layer 5.
本発明の目的は、ＰＮ接合分離での分離拡散のような長
時間の高温熱処理をしないで半導体装置の表面から半導
体基板にアースをとることのできる半導体装置の製造方
法を提供することである。An object of the present invention is to provide a method for manufacturing a semiconductor device that can connect the surface of the semiconductor device to the semiconductor substrate without performing long-term high-temperature heat treatment such as separation diffusion in PN junction separation.
本発明の別の目的は、ＶＩＰ絶縁層分離構造を半導体基
板アースに利用した半導体装置の製造方法を提供するこ
とである。Another object of the present invention is to provide a method for manufacturing a semiconductor device using a VIP insulating layer isolation structure for grounding a semiconductor substrate.
上述の目的が、−導電型半導体基板上に反対導−ｗｔｍ
ｘ−ヒタキシャル層を形成し、仁のエピタキシャル層表
面から前記半導体基板に達する纒を形成し、溝の底部に
選択的に耐酸化膜を配設し、この耐酸化膜をマスクとし
て酵内の半導体層底面を酸化し、耐酸化膜を除去して溝
内に半導体基板の一部を表出し、溝内に一導電製不純物
を含む半導体層を配設し、そして熱処理を行なって半導
体層中の不純物を半導体基板へ拡散する工程を有するこ
とを特徴とする半導体装置の製造方法によって達成する
仁とができる。The above-mentioned purpose is to provide - opposite conductivity on a conductivity type semiconductor substrate - wtm
An x-hytaxial layer is formed, a thread is formed extending from the surface of the epitaxial layer to the semiconductor substrate, an oxidation-resistant film is selectively provided at the bottom of the groove, and the oxidation-resistant film is used as a mask to protect the semiconductor in the fermenter. The bottom surface of the layer is oxidized, the oxidation-resistant film is removed to expose a part of the semiconductor substrate in the trench, a semiconductor layer containing a conductive impurity is placed in the trench, and heat treatment is performed to remove the oxidation-resistant film. This can be achieved by a method for manufacturing a semiconductor device characterized by including a step of diffusing impurities into a semiconductor substrate.
溝形成後から一導電製不純物を含む半導体層を配設する
前までを詳しく述べると、例えば、次のような工程■〜
（ハ）：
（７）エピタキシャル成長層および半導体基板のＶ溝露
出表面を熱酸化によって薄−二酸化シリコン（８１０２
） ＩＩ！を形成する、
（イ）形成した５ｔｏｚ膜の上に耐酸化膜である窒化膜
を形成する、
（勿 この窒化膜の上に多結晶シリコン＃（例えば２０
００Ｘ厚）を薄く形成し、熱酸化によってこの多結晶シ
リコン膜をＶ溝先端部を除−て酸化して８１０２展を形
成する、
に） ８１０２膜を除去し、酸化されなかった多結晶シ
リコン膜を残す、
に）■溝先端部に残っている多結晶シリ；ン膜をマスク
とし′てｖ溝斜面上の窒化膜を除去する、（ホ）熱酸化
に′よってＶ溝斜面をさらに酸化して８１０２ Ｍを厚
くする、および
（至）残らている多結晶シリコン膜、Ｉｌ化膜およびそ
の下の薄い８１０２膜を除去する、で行なうことができ
る。To describe in detail the process from after trench formation to before disposing a semiconductor layer containing a conductive impurity, for example, the following steps
(c): (7) The epitaxial growth layer and the exposed surface of the V-groove of the semiconductor substrate are thermally oxidized to form a thin layer of silicon dioxide (8102
) II! (a) Form a nitride film, which is an oxidation-resistant film, on the formed 5TOZ film. (Of course, polycrystalline silicon # (for example, 20
00X thickness) and oxidize this polycrystalline silicon film by thermal oxidation except for the tip of the V groove to form an 8102 film. 2) Remove the nitride film on the V-groove slope by using the polycrystalline silicon film remaining at the groove tip as a mask. (e) Further oxidize the V-groove slope by thermal oxidation. This can be done by increasing the thickness of the 8102M film and removing the remaining polycrystalline silicon film, the Illide film, and the thin 8102 film thereunder.
以下、本発明に係る半導体装置および゛その製造方法を
添付図面を参照して詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
例えばＰ型のシリコン半導体基板１１（第２図）の上に
Ｎ型のシリコンエピタキシャル成長膜（例えば厚さ２．
４μｍ）１２を形成し、このエピタキシャル成長層の表
面に熱酸化法又はＣＶＤ （（Ｔｈ＠ｍ１ｅａｌＶａｐ
ｏｕｒ Ｄ＠ｐｏｓｉｔｉｏｎ ）法によって二酸化シ
リコン（Ｓ魚０２）膜１３（例えば厚さ１５００り、続
いてｃｖｎ法によって窒化シリコン（８１３Ｎ４）７１
１１１４（例えば厚さ２８００Ｘ）を形成する。次にホ
トエツチング法によってｖ＃ｌ形成領域の窒化シリコン
［４および二酸化シリコン膜１３を選択エツチングし、
さらに異方性エツチングによってエピタキシャル成長層
１２および基ｉ／ｋ１１に第２図に示したようにＶ溝を
形成する。熱酸化法によってＶ＠の表面（斜面）を酸化
して薄い二酸化シリコン膜１５（例えば厚さ５００芙）
を形成する（第２図）。For example, on a P-type silicon semiconductor substrate 11 (FIG. 2), an N-type silicon epitaxial growth film (for example, 2.5 mm thick) is formed.
4 μm) 12 is formed, and the surface of this epitaxial growth layer is subjected to thermal oxidation or CVD ((Th@m1ealVap
A silicon dioxide (S02) film 13 (for example, 1,500 mm thick) is formed by the our D@position method, and then a silicon nitride (813N4) film 71 is formed by the CVN method.
1114 (for example, thickness 2800X). Next, the silicon nitride film 4 and the silicon dioxide film 13 in the v#l formation region are selectively etched using a photoetching method.
Furthermore, a V-groove is formed in the epitaxial growth layer 12 and the base i/k 11 by anisotropic etching as shown in FIG. The surface (slope) of V@ is oxidized by a thermal oxidation method to form a thin silicon dioxide film 15 (for example, 500 mm thick).
(Figure 2).
ＣＶＤ法によって窒化シリコン膜１６（例えば厚さ８Ｏ
−ＯＸ）をＶ溝内の二酸化シリコン膜１５および先に形
成した窒化シリコン膜１４の上に堆積形成する（第３図
）。Ｖ溝の外の窒化膜１４は合計厚さく３６００Ｘ）と
なる。続いて、ＣＶＤ法によって多結晶シリコン膜（例
えば厚さ２０００１）を窒化シリコン膜上に形成し、こ
の多結晶シリコン膜を熱酸化によって酸化して二酸化シ
リコン族１７（厚さ４０００Ｘ）を形成する。この熱酸
化の際−にｖｎ先端部分の多結晶シリコン［１８は酸化
されずに第３図に示したように残る。、次に、二酸化シ
リコン膜１７をエツチング液（）、酸系溶液）にて除去
して多結晶シリコン膜１８および窒化シリコン膜が表出
する。続いて窒化シリコン膜１６を工、テンダ液（リン
酸沸騰溶液）にて除去する。このとき残っている多結晶
シリコン［１８がマスクとなってＶ溝先端部に窒化シリ
コン膜１６の一部が残り、またＶ溝の外の窒化膜１４は
エツチングによって薄（なシ当初の厚さとなる（第４図
）。A silicon nitride film 16 (for example, 80 mm thick) is formed by the CVD method.
-OX) is deposited on the silicon dioxide film 15 in the V-groove and the previously formed silicon nitride film 14 (FIG. 3). The total thickness of the nitride film 14 outside the V-groove is 3600×). Subsequently, a polycrystalline silicon film (for example, 20001× in thickness) is formed on the silicon nitride film by CVD, and this polycrystalline silicon film is oxidized by thermal oxidation to form silicon dioxide group 17 (4000× in thickness). During this thermal oxidation, the polycrystalline silicon [18] at the tip of the VN is not oxidized and remains as shown in FIG. Next, the silicon dioxide film 17 is removed using an etching solution (1) or an acid-based solution to expose the polycrystalline silicon film 18 and the silicon nitride film. Subsequently, the silicon nitride film 16 is removed using a tender solution (boiling phosphoric acid solution). At this time, the remaining polycrystalline silicon [18] serves as a mask, and a portion of the silicon nitride film 16 remains at the tip of the V-groove, and the nitride film 14 outside the V-groove is thinned by etching (not as thin as the original thickness). (Figure 4).
多結晶シリコン膜１８を除去し、熱酸化によ、ってｖ＃
１表面の薄い二酸化シリコン膜１５を通してエピタキシ
ャル成長層１２および基板１１を酸化して比較的厚い二
酸化シリコン膜１９（例えば厚さ５０００１）を形成す
る（第５図）。Polycrystalline silicon film 18 is removed and thermal oxidation is performed to v#
The epitaxial growth layer 12 and substrate 11 are oxidized through the thin silicon dioxide film 15 on one surface to form a relatively thick silicon dioxide film 19 (eg, 50,001 mm thick) (FIG. 5).
■溝の先端に残つている窒化シリコン膜１６をエツチン
グ除去する。このとき、窒化シリコン膜１４も厚さが減
少するが除去してはいけない。続いて、■溝先端にある
薄い二酸化シリコンＭ１５を工、チング除去して半導体
基板１１を表出する。(2) The silicon nitride film 16 remaining at the tip of the trench is removed by etching. At this time, the thickness of the silicon nitride film 14 is also reduced, but it must not be removed. Subsequently, (2) the thin silicon dioxide M15 at the tip of the groove is etched and removed to expose the semiconductor substrate 11;
この工、チングによってＶ溝表面の比較的厚い二酸化シ
リコン膜１９も厚さが約５００Ｘだけ減少する。次に、
ＣＶＤ法によって不純物（例えばポロン）をドーグしな
がら多結晶シリコンをＶ溝を埋める程厚く形成し、う、
ピンクによってＶ溝内にのみこの多結晶シリコン２０を
残して他を除去する（第６図）。もちろん多結晶シリコ
ン成長後、う、ピングしてから不純物をドーグしてもか
まわない。ラッピングの際に窒化シリコン膜１４がス・
トッノ々として働く。Due to this etching, the relatively thick silicon dioxide film 19 on the V-groove surface is also reduced in thickness by about 500X. next,
By doping impurities (for example, poron) using the CVD method, polycrystalline silicon is formed thick enough to fill the V-groove.
The polycrystalline silicon 20 is left only in the V-groove and the rest is removed using pink color (FIG. 6). Of course, after polycrystalline silicon is grown, impurities may be doped after pinging. During lapping, the silicon nitride film 14 is
Work as a tonnō.
そして、多結晶シリコン２０の表面を熱酸化して厚い二
酸化シリコン膜２１（例えば厚さ８０００Ｘ）を形成す
る。この熱処理によって多−品シリコン２０内にドーグ
されていた不純物（ポロン）がＶ溝先端部で半導体基板
１１内へ拡散し、またトランジスタのベース、エミ、り
などを形成する際の熱処理によっても拡散して第７図の
破線で示した領域２２へ広がる。この拡散領域２２はチ
ャネルカットもかねている。表面の二酸化シリコンｄ２
１にコンタクトのための開孔をホトエツチング法で形成
し、アース゛−極２３を形成する。このようにして基板
にアースをとることができ、本発明に係る半導体装置が
得られる。Then, the surface of the polycrystalline silicon 20 is thermally oxidized to form a thick silicon dioxide film 21 (eg, 8000× thick). Due to this heat treatment, the impurity (poron) doped in the multi-component silicon 20 is diffused into the semiconductor substrate 11 at the tip of the V-groove, and is also diffused by the heat treatment when forming the base, emitter, rib, etc. of the transistor. Then, it spreads to a region 22 indicated by a broken line in FIG. This diffusion region 22 also serves as a channel cut. silicon dioxide d2 on the surface
A hole for a contact is formed in 1 by photo-etching, and a ground electrode 23 is formed. In this way, the substrate can be grounded, and a semiconductor device according to the present invention can be obtained.
図面上にはトランジスタ等の能動素子や受動素子および
埋込層を示していないが、通常の公知方法によりてこれ
らが形成される。Although active elements such as transistors, passive elements, and buried layers are not shown in the drawings, they are formed by conventional known methods.
第１図は、ＶＩＰ絶縁層分離構造を有する半導体装置の
部分断面図であシ、第２図ないし第７図は本発明に係る
半導体装置の製造方法を説明する半導体装置の部分断面
図である。
１１・・・半導体基板、１２・・・エピタキシャル成長
層、１３・・・二酸化シリコン膜、１４−・・窒化シリ
コン膜、１５・・・二酸化シリコン膜、１６−・・窒化
シリコン膜、１８・・・多結晶シリコン、１９・−二酸
化シリコン膜、２０・・・多結晶シリコン、２２・−拡
散領域、２３・・・アース電極。
１５
第６図
′２２FIG. 1 is a partial cross-sectional view of a semiconductor device having a VIP insulating layer isolation structure, and FIGS. 2 to 7 are partial cross-sectional views of a semiconductor device for explaining a method of manufacturing a semiconductor device according to the present invention. . DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... Epitaxial growth layer, 13... Silicon dioxide film, 14-... Silicon nitride film, 15... Silicon dioxide film, 16-... Silicon nitride film, 18... Polycrystalline silicon, 19.--silicon dioxide film, 20.--polycrystalline silicon, 22.--diffusion region, 23.-- earth electrode. 15 Figure 6'22
Claims (1)
形成し、次いで前記エピタキシャル層表面から前記半導
体基板に達する溝を形成し、次いで前記溝の底部に選択
的に耐酸化膜を配設し、次いで前記耐酸化膜をマスクと
して前記溝内の半導体層表面を酸化し、次いで前記耐酸
化膜を除去して前記溝内に半導体基板の一部を表出し、
次いで前記溝内に一導電型不純物を含む半導体層を配設
し、次いで熱処理を行なって前記半導体層中の不純物を
前記半導体基板へ拡散する工程を有することを特徴とす
る半導体装置の製造方法。An epitaxial layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, a groove is formed from the surface of the epitaxial layer to the semiconductor substrate, an oxidation-resistant film is selectively provided at the bottom of the groove, and then oxidizing the surface of the semiconductor layer in the groove using the oxidation-resistant film as a mask, then removing the oxidation-resistant film to expose a part of the semiconductor substrate in the groove;
A method for manufacturing a semiconductor device, comprising the steps of: next disposing a semiconductor layer containing impurities of one conductivity type in the groove; and then performing heat treatment to diffuse the impurities in the semiconductor layer into the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14775181A JPS5850752A (en) | 1981-09-21 | 1981-09-21 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14775181A JPS5850752A (en) | 1981-09-21 | 1981-09-21 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5850752A true JPS5850752A (en) | 1983-03-25 |
| JPH0234179B2 JPH0234179B2 (en) | 1990-08-01 |
Family
ID=15437317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14775181A Granted JPS5850752A (en) | 1981-09-21 | 1981-09-21 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850752A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0221394A2 (en) * | 1985-10-31 | 1987-05-13 | International Business Machines Corporation | Method of making an integrated circuit structure |
| JPS63116445A (en) * | 1986-11-04 | 1988-05-20 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
| US4835586A (en) * | 1987-09-21 | 1989-05-30 | Siliconix Incorporated | Dual-gate high density fet |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5525501A (en) * | 1978-08-04 | 1980-02-23 | Supensaa Hetsuzu Inc | Insert for ignition deck of internal |
-
1981
- 1981-09-21 JP JP14775181A patent/JPS5850752A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5525501A (en) * | 1978-08-04 | 1980-02-23 | Supensaa Hetsuzu Inc | Insert for ignition deck of internal |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0221394A2 (en) * | 1985-10-31 | 1987-05-13 | International Business Machines Corporation | Method of making an integrated circuit structure |
| US4745081A (en) * | 1985-10-31 | 1988-05-17 | International Business Machines Corporation | Method of trench filling |
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
| JPS63116445A (en) * | 1986-11-04 | 1988-05-20 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US4835586A (en) * | 1987-09-21 | 1989-05-30 | Siliconix Incorporated | Dual-gate high density fet |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0234179B2 (en) | 1990-08-01 |
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