JPH0650740B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0650740B2 JPH0650740B2 JP14856386A JP14856386A JPH0650740B2 JP H0650740 B2 JPH0650740 B2 JP H0650740B2 JP 14856386 A JP14856386 A JP 14856386A JP 14856386 A JP14856386 A JP 14856386A JP H0650740 B2 JPH0650740 B2 JP H0650740B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- field insulating
- region
- semiconductor device
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に高周波トランジスタを
有する半導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high frequency transistor.
従来、高周波トランジスタの引出し電極を形成するとき
には、電気容量を小さするために引出し電極は厚いフィ
ールド絶縁膜の上に形成していた。そして、第２図に示
すようにこのフィールド絶縁膜１よりも内側の活性領域
にＰ型ベース領域２とＮ型エミッタ領域５からなる浅い
Ｐ−Ｎ接合を選択的に形成し、更に電極６を形成してト
ランジスタを製作していた。Conventionally, when forming the extraction electrode of a high frequency transistor, the extraction electrode has been formed on a thick field insulating film in order to reduce the electric capacity. Then, as shown in FIG. 2, a shallow PN junction consisting of the P-type base region 2 and the N-type emitter region 5 is selectively formed in the active region inside the field insulating film 1, and the electrode 6 is further formed. It was formed to make a transistor.
上述した従来の半導体素子の構造では、フィールド絶縁
膜１を選択的に形成した場合、その後の熱処理などによ
ってフィールド絶縁膜１の境界付近から結晶欠陥が発生
した。そのため、活性領域にトランジスタ等を形成して
いくときに、結晶欠陥の影響を受けて半導体素子等の例
えば、コレクタ・ベースのＰ−Ｎ接合特性が悪化してリ
ーク電流が発生し、半導体素子の歩留を大きく下げると
いう問題点があった。In the structure of the conventional semiconductor device described above, when the field insulating film 1 is selectively formed, a crystal defect occurs near the boundary of the field insulating film 1 due to the subsequent heat treatment or the like. Therefore, when a transistor or the like is formed in the active region, a PN junction characteristic of a semiconductor element or the like, for example, a collector-base is deteriorated due to the influence of crystal defects, and a leak current is generated. There was a problem that the yield was greatly reduced.
本発明の目的は、結晶欠陥をなくしてリーク電流を少く
した製造歩留りの高い半導体装置を提供することにあ
る。It is an object of the present invention to provide a semiconductor device having a high manufacturing yield, which eliminates crystal defects and reduces leakage current.
本発明の半導体装置は、半導体基板上に選択的にフィー
ルド絶縁膜を形成し、このフィールド絶縁膜の境界付近
の半導体基板表面をエッチングし、このエッチングされ
た領域にゲッタ作用を有する不純物を導入したものであ
る。In the semiconductor device of the present invention, a field insulating film is selectively formed on a semiconductor substrate, the surface of the semiconductor substrate near the boundary of the field insulating film is etched, and impurities having a getter action are introduced into the etched region. It is a thing.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第１図において、Ｎ＋型シリコン基板４上のＮ型エピキ
シャル層３には選択的にSiO2からなるフィールド絶縁膜
１が形成されており、このフィールド絶縁膜１に囲まれ
た活性領域中には、Ｐ型ベース領域２、Ｎ型エミッタ領
域５、電極６等からなるトランジスタが形成されてい
る。そしてフィールド絶縁膜１と活性領域との境界付近
はエッチングされており、その部分はゲッタ作用を有す
るリンが導入されたＮ＋型拡散領域となっている。In FIG. 1, a field insulating film 1 made of SiO 2 is selectively formed on an N type epitaxial layer 3 on an N + type silicon substrate 4, and an active region surrounded by the field insulating film 1 is formed in the active region. In, a transistor including a P-type base region 2, an N-type emitter region 5, an electrode 6 and the like is formed. Then, the vicinity of the boundary between the field insulating film 1 and the active region is etched, and that portion is an N + type diffusion region into which phosphorus having a getter action is introduced.
このように構成された本実施例においては、フィールド
絶縁膜１の境界付近はエッチングされ、更にゲッタ作用
を有するリンを含むＮ＋型拡散層７が設けられているた
め、活性領域中の結晶欠陥は除去される。従って、活性
領域中に形成されるトランジスタのＰ−Ｎ特性は良好と
なり、製造歩留りは向上する。In this embodiment having such a structure, the vicinity of the boundary of the field insulating film 1 is etched, and the N + type diffusion layer 7 containing phosphorus having a gettering action is further provided, so that a crystal defect in the active region is formed. Are removed. Therefore, the P-N characteristics of the transistor formed in the active region are good, and the manufacturing yield is improved.
次に、本発明の一実施例の製造方法について説明する。Next, a manufacturing method according to an embodiment of the present invention will be described.
まずＮ＋型シリコン基板４上にＮ型エピタキシャル層２
の表面に薄い酸化膜を形成し、更にその上にSi3N4膜を
薄く形成する。そして、フォトリソグラフィ技術を用い
て部分的にSi3N4膜を取り除いたのち、その表面を高温
度で加圧酸化をし部分的に酸化膜の厚いフィールド絶縁
膜１を形成する。このときの酸化膜の厚さはトランジス
タの特性によって異なるが約１〜1.5μｍ程度である。
このようなフィールド絶縁膜１を形成するときに、その
境界付近に結晶欠陥が発生し、この欠陥は後の工程でト
ランジスタの特性に大きな影響をあたえるため、フォト
リソグラフィの技術を用いて選択的にSi3N4膜を取り除
き、ドライエッチング技術を用いてシリコンの結晶欠陥
の多いフィールド絶縁膜１の境界付近を選択的に除去
し、ＨＦ処理をした後不純物としてリンを拡散し将来ト
ランジスタを形成していくときのゲッタリング作用を持
たせるＮ＋型拡散領域７を形成する。First, the N type epitaxial layer 2 is formed on the N + type silicon substrate 4.
A thin oxide film is formed on the surface of, and a Si 3 N 4 film is further formed thereon. Then, the Si 3 N 4 film is partially removed by using the photolithography technique, and the surface thereof is subjected to pressure oxidation at a high temperature to form the field insulating film 1 having a partially thick oxide film. The thickness of the oxide film at this time is about 1 to 1.5 μm, although it depends on the characteristics of the transistor.
When such a field insulating film 1 is formed, a crystal defect is generated in the vicinity of the boundary, and since this defect has a great influence on the characteristics of the transistor in a later step, the photolithography technique is selectively used. The Si 3 N 4 film is removed, the vicinity of the boundary of the field insulating film 1 with many crystal defects of silicon is selectively removed by using the dry etching technique, and after HF treatment, phosphorus is diffused as an impurity to form a transistor in the future. An N + type diffusion region 7 having a gettering action when moving is formed.
その後、Si3N4と薄い酸化膜を除去し、表面を洗浄した
後酸化膜を形成しフォトリソグラフィの技術を用い、酸
化膜を選択的に除去し、ホウ素を拡散してトランジスタ
のＰ型ベース領域２を形成する。その後表面を再度酸化
し、フォトリソグラフィの技術を用いて開孔部を形成
し、Ｎ型エミッタ領域５及び電極６を形成しトランジス
タを完成させる。After that, the Si 3 N 4 and the thin oxide film are removed, the surface is washed, and then the oxide film is formed, and then the oxide film is selectively removed by using the photolithography technique. Region 2 is formed. After that, the surface is oxidized again, an opening is formed by using the photolithography technique, the N-type emitter region 5 and the electrode 6 are formed, and the transistor is completed.
尚、上記実施例においてバイポーラトランジスタを用
い、ゲッタ作用を有する不純物としてリンを用いた場合
について説明したが、ＭＯＳトランジスタであってもよ
く、又不純物としてはヒ素やヒ素とリンを用いることが
できる。In the above embodiments, the bipolar transistor is used and phosphorus is used as the gettering impurity. However, a MOS transistor may be used, and arsenic or arsenic and phosphorus may be used as the impurities.
以上説明したように本発明は、フィールド絶縁膜を選択
的に形成し、その境界付近の結晶欠陥の多い領域をドラ
イエッチング法で除去し、更にその領域に不純物を拡散
させゲッタリング作用を持たせることにより、トランジ
スタのＰ−Ｎ接合を良好なものとし、リンク電流を非常
に少なくすることができる効果がある。従って、半導体
装置の製造歩留りは向上したものとなる。As described above, according to the present invention, a field insulating film is selectively formed, a region with many crystal defects near the boundary is removed by a dry etching method, and an impurity is diffused in the region to give a gettering action. As a result, the P-N junction of the transistor is improved, and the link current can be extremely reduced. Therefore, the manufacturing yield of the semiconductor device is improved.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置の一例の断面図である。 １……フィールド絶縁膜、２……Ｐ型ベース領域、３…
…Ｎ型エピタキシャル層、４……Ｎ＋型シリコン基板、
５……Ｎ型エミッタ領域、６……電極、７……Ｎ＋型拡
散領域。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. 1 ... Field insulating film, 2 ... P-type base region, 3 ...
... N type epitaxial layer, 4 ... N + type silicon substrate,
5 ... N-type emitter region, 6 ... Electrode, 7 ... N + type diffusion region.
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/73 Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 29/73
Claims (1)
を形成し、該フィールド絶縁膜の境界付近の前記半導体
基板表面をエッチングし、該エッチングされた領域にゲ
ッタ作用を有する不純物を導入したことを特徴とする半
導体装置。1. A field insulating film is selectively formed on a semiconductor substrate, the surface of the semiconductor substrate near the boundary of the field insulating film is etched, and impurities having a getter action are introduced into the etched region. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14856386A JPH0650740B2 (en) | 1986-06-24 | 1986-06-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14856386A JPH0650740B2 (en) | 1986-06-24 | 1986-06-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS633420A JPS633420A (en) | 1988-01-08 |
| JPH0650740B2 true JPH0650740B2 (en) | 1994-06-29 |
Family
ID=15455547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14856386A Expired - Lifetime JPH0650740B2 (en) | 1986-06-24 | 1986-06-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650740B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023156859A1 (en) | 2022-02-15 | 2023-08-24 | 株式会社寺岡精工 | Weighing device, sales system, and display device |
-
1986
- 1986-06-24 JP JP14856386A patent/JPH0650740B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023156859A1 (en) | 2022-02-15 | 2023-08-24 | 株式会社寺岡精工 | Weighing device, sales system, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS633420A (en) | 1988-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4408387A (en) | Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask | |
| US4343080A (en) | Method of producing a semiconductor device | |
| US5198692A (en) | Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions | |
| US5763931A (en) | Semiconductor device with SOI structure and fabrication method thereof | |
| JPH0650740B2 (en) | Semiconductor device | |
| JPH05102175A (en) | Manufacture of semiconductor device | |
| JP2858510B2 (en) | Method for manufacturing semiconductor device | |
| JP2633374B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH05235009A (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP2633411B2 (en) | Method for manufacturing semiconductor device | |
| KR960013942B1 (en) | Manufacturing method of self-aligned dipole transistor | |
| JP2546651B2 (en) | Method of manufacturing bipolar transistor | |
| JPS6018951A (en) | Manufacture of semiconductor device | |
| JPH05326857A (en) | Manufacture of semiconductor device | |
| JPH04152531A (en) | Manufacturing method of semiconductor device | |
| JPH05129426A (en) | Element isolation method of semiconductor device | |
| JPS63173357A (en) | Manufacture of semiconductor device | |
| JPH04309232A (en) | Bipolar transistor and its manufacture | |
| JPS5846857B2 (en) | Manufacturing method of semiconductor device | |
| JPH05102172A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01214156A (en) | Bipolar memory | |
| JPS6110251A (en) | Semiconductor device | |
| JPS6222451A (en) | P-n junction isolation method of semiconductor substrate | |
| JPH01189159A (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPH0786418A (en) | Method of manufacturing semiconductor device and semiconductor device |