JPH10261647A - Bipolar semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve dimensional precision of a base region formed by selective epitaxial growth and to improve the uniformly of a characteristic. SOLUTION: A collector region 3 is formed on the surface side of a semiconductor substrate 1, and the surface is partially opened. First insulating films 7 are formed, and the first insulating films 7 second insulating films 8 and conductive layers 9 becoming base extraction electrode layers are stacked sequentially. The outer parts of the conductive layers 9 are patterned, and opening which are much smaller are formed on the inner sides of the opening parts in the conductive layers 9. At the time of displaying a collector region 3 by isotropically etching the second insulating films 8 through the opening parts of the conductive layers 9, the opening end faces of the first insulating films 7 are partially exposed to the lower side of the end parts of the conductive layers 9 and the base region 12 is formed on the exposed surface of the collector region 3 by an epitaxial growth method, by embedding space at the lower side of the end parts of the conductive layers 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bipolar semiconductor device capable of improving the dimensional accuracy of a base region formed by epitaxial growth, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a method of realizing a high-speed bipolar transistor by reducing the parasitic capacitance of a base, an SSSB (Su
per Self-aligned Selectiely grown Base) and a technique for forming a base region disclosed in Japanese Patent Application Laid-Open No. 05-074789.

FIG. 7 is a sectional view showing a method of manufacturing a bipolar semiconductor device disclosed in Japanese Patent Application Laid-Open No. 05-074789. First, in FIG. 7A, after a field insulating film 100 and a collector region 101 are formed on a semiconductor substrate, a thin first insulating film 102 is formed on the surface of the collector region 101.
And a P-type polysilicon film 103, a refractory metal silicide 104, and a second
Are sequentially formed. Then, after opening the second insulating film 105, the refractory metal silicide 104, and the P-type polysilicon film 103, the first insulating film 102 is isotropically etched by wet etching to form the P-type polysilicon film 103. From the edge of a distance d.

[0004] In FIG. 7 (b), the surface of the collector region 101 exposed by isotropic etching of the first insulating film 102 is
A selective epitaxial base 106 is grown. As a result, the selective epitaxial base 106 is connected to the P-type polysilicon film 103 so as to fill the eave-shaped space formed below the end of the P-type polysilicon film 103. After that, a third insulating film 107 is formed on the side wall of the opening,
A second polysilicon 108 connected to the surface of the selective epitaxial base 106 sandwiched between the third insulating films 107 is formed to form an emitter region.

In this manufacturing method, the first insulating film 102 protects the surface of the collector region 101 during dry etching for opening the refractory metal silicide 104 and the P-type polysilicon film 103, thereby preventing the introduction of damage. .
Further, since the first insulating film 102 is interposed between the first insulating film 102 and the collector region 101 around the opening of the P-type polysilicon film 103, the first insulating film 102 can be transferred from the P-type polysilicon film 103 to the collector region 101 even after a subsequent heat treatment. There is no diffusion of impurities.

[0006]

However, in this conventional method for manufacturing a bipolar semiconductor device, the first insulating film 102 is isotropically etched by wet etching.
The formation region of the base region (selective epitaxial base 106) is determined by this etching amount. For this reason, the distance d of the eaves is determined due to variations in the wettability and the ease of penetration of the etchant for etching the first insulating film 102.
Is difficult to keep constant, and therefore the size of the selective epitaxial base 106 tends to vary. as a result,
Variations in the base resistance and junction capacitance of the resulting bipolar semiconductor device were large, which was a major factor in the variation in high frequency characteristics. That is, the conventional method of manufacturing a bipolar semiconductor device has a problem that a high-performance bipolar transistor cannot be manufactured stably.

The present invention has been made in view of the above circumstances, and provides a bipolar semiconductor device in which the dimensional accuracy of a base region formed by epitaxial growth is improved, thereby improving the uniformity of characteristics, and a method of manufacturing the same. The purpose is to provide.

[0008]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a method of manufacturing a bipolar semiconductor device according to the present invention isotropically prior to epitaxial growth of a base region. An insulating film (first insulating film) previously opened in a predetermined shape is interposed between the insulating film (second insulating film) to be etched and the collector region, and the opening size of the first insulating film depends on the opening size. The dimensions of the base region are determined.

That is, according to the method of manufacturing a bipolar semiconductor device of the present invention, a collector region is formed on a front surface side of a semiconductor substrate, and a first insulating film is formed by partially opening the surface of the collector region. A second insulating film made of a film material having an etching rate higher than that of the first insulating film, and a conductive layer serving as a base extraction electrode layer are sequentially laminated, and the conductive film outside an opening portion of the first insulating film is laminated. Patterning the outer periphery of the layer, and then forming a slightly smaller opening inside the opening of the first insulating film for the conductive layer covering the opening of the first insulating film; When the collector region is exposed by isotropically etching the second insulating film through the opening, the opening end surface of the first insulating film is at least partially positioned below the end of the conductive layer. To express, The exposed surface of the serial collector region, a base region connected to the conductive layer in the form to fill the end lower side of the space of the conductive layer is formed by epitaxial growth method.

According to this manufacturing method, the isotropic etching of the second insulating film is performed until the opening end face of the first insulating film that has been opened is exposed. After the end surface is exposed, the exposed surface of the collector region does not spread any more. Because this first
This is because the insulating film is made of a film material having a high etching selectivity with respect to the second insulating film. Therefore, the base region epitaxially grown on the exposed surface of the collector region thereafter has a uniform size.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bipolar transistor according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a sectional view showing the structure of a bipolar transistor according to this embodiment. In FIG. 1, reference numeral 1 denotes a p-type semiconductor substrate such as a silicon wafer, 2 denotes an n ⁺ collector buried region,
3 is an n-type collector region, 4 is a deep LOCOS (Local O
xidation of Silicon), 5 is an n ⁺ diffusion region, and 6 is a p ⁺ diffusion region for element isolation.

[0013] A first insulating film 7 is formed on the flattened surfaces of the collector region 3, the n ⁺ diffusion region 5 and the deep LOCOS 4, and is opened on the collector region 3. Although the material of the first insulating film 7 is not particularly limited, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are selected.
Further, a second insulating film 8 is formed on the first insulating film 7. The second insulating film 8 partially covers the opening end surface (side surface) of the first insulating film 7 or the first insulating film 7
And is not in contact with the collector region 3. The first insulating film 7 is made of a material having a higher etching rate than the second insulating film 8. For example, when the first insulating film 7 is a silicon nitride film or a silicon oxynitride film, the second insulating film 8 is made of a silicon oxide film, PS
A silicon oxide film containing impurities such as G and BPSG can be selected. When the first insulating film 7 is a silicon oxide film, a silicon oxide film containing impurities can be selected as the second insulating film 8. In addition, as the first insulating film 7, II
An amorphous compound of a group I element and a group V element (for example, GaAs
The film of s) can also be used, and in this case, a silicon oxide film can be selected as the second insulating film 8.

On the second insulating film 8, p is formed so as to protrude from the upper surface of the second insulating film 8 into the opening of the first insulating film 7.
A first polysilicon film 9 into which a type impurity has been introduced extends. Further, a high melting point metal silicide layer 10 is formed on the first polysilicon film 9. The refractory metal silicide layer 10 is formed for reducing the resistance, but may be omitted if not necessary. On the refractory metal silicide layer 10, a third insulating film 11 made of, for example, a silicon oxide film or the like is formed.

In the opening of the first insulating film 7, a base region 12 into which a p-type impurity is introduced is formed by selective epitaxial growth. The base region 12 is formed so as to surround the surface of the first polysilicon film 9 which protrudes into the opening of the first insulating film 7 and to contact the entire surface of the collector region 3 in the opening. ing. On the base region 12, a side wall spacer 13 that covers the opening side wall of the refractory metal silicide layer 10 and the third insulating film 11 is formed. An emitter region 14 into which an n-type impurity is introduced is formed at a surface side portion of the base region 12 surrounded by the sidewall spacer 13, and the sidewall spacer 13 and the third insulating film are formed on the emitter region 14. 11, a second polysilicon film 15 serving as an emitter extraction electrode is formed.

In the bipolar transistor having such a structure, the shape of the base region 12, particularly the collector region 3
Is determined by the size of the opening of the first insulating film 7. Therefore, there is an advantage that the junction capacitance and the base resistance between the base and the collector are constant, and the uniformity of the high frequency characteristics is high.

Next, a method of manufacturing a bipolar transistor according to the present invention will be described with reference to cross-sectional views of respective manufacturing steps shown in FIGS. A bipolar transistor is usually manufactured by first forming a collector region on a semiconductor substrate, separating elements, forming a base and emitter region, and forming an extraction electrode. FIG.
FIG. 5 to FIG. 5 show after the formation of the base and emitter regions,
The formation of the collector region and the element isolation are only denoted by reference numerals, and the specific formation procedure is not shown.

The formation of the collector region and the element isolation are performed according to a conventional method. First, a p-type semiconductor substrate 1
And a collector buried region 2 is formed on the surface of the semiconductor substrate 1. The collector buried region 2 is formed by introducing an n-type impurity at a high concentration by, for example, selective gas phase diffusion using a silicon oxide film or the like as a mask. After removing the silicon oxide film, an n-type epitaxial layer (collector region 3) is formed on the surface of the substrate by an ordinary method. The resistivity of this collector region is 0.3-5.0 Ωcm
And the thickness is about 0.5 to 2.5 μm. afterwards,
In the n-type collector region 3, a deep LOCOS 4 made of a silicon oxide film or the like is formed in the element isolation region. Deep LOCOS 4 can be realized by the recessed LOCOS method. That is, first, a thin buffer oxide film such as a silicon oxide film and an oxidation prevention film such as a silicon nitride film are laminated in this order, and after opening a predetermined patterning window, RIE (Reac
Anisotropic etching such as tive ion etching is performed to form a recess in the collector region 3. Then, LOCOS oxidation is performed, and thereafter, only the oxidation prevention film on the surface is removed. With the thin buffer oxide film remaining, an n ⁺ impurity diffusion region 5 for taking out the collector electrode is formed. This n ⁺
To form the impurity diffusion region 5, first, a resist pattern having an opening on one side of the LOCOS 4 is formed, and phosphorus (P ⁺ ) is ion-implanted using the resist pattern as a mask.
After accumulating the silicon oxide film, annealing is performed and thermal diffusion is performed. At this stage, in order to smooth the bird's head of the LOCOS 4, a smoothing resist is applied, and RIE is performed under the condition that the bird's head is smoothed.
Thereafter, if the remaining silicon oxide film is removed by wet etching or the like, a flattened surface as shown in FIG. 2 is obtained. Then, a resist pattern having an opening with a predetermined width is formed on the LOCOS 4, and using this resist pattern as a mask,
Boron (B ⁺ ) is ion-implanted under predetermined conditions to form ap ⁺ impurity region 6 for element isolation on the deep side of the LOCOS 4 in the substrate. When the resist is removed, element isolation is completed.

The subsequent steps will be described with reference to FIGS. In FIG. 2, first, the first insulating film 7 is formed to a thickness of about 50 to 200 nm. And
A resist pattern is formed in a portion to be a base formation region on the collector region 3, and the first insulating film 7 is etched by RIE or the like to form an opening 7a of the first insulating film 7. Next, a second insulating film 8 is formed on the entire surface to a thickness of about 20 to 60 nm. As the second insulating film 8, a film material having an etching rate higher than that of the first insulating film 7 is used. Thereby, the surface of the collector region 3 in the opening 7a is coated.

Next, the first polysilicon film 9 is
It is deposited on the entire surface by the D method. Thereafter, boron (B ⁺ ) or boron fluoride (BF ₂ ⁺ ) is ion-implanted to convert the polysilicon film 9 into a p-type (conductivity). This ion implantation is performed when the ion species is BF ₂ ⁺ , for example, energy: 2
0 keV to 70 keV, dose amount: 1 × 10 ¹⁵ to 1 × 1
Perform under the condition of 0 ¹⁶ . Note that there is also a conductive method in which an impurity is introduced during CVD. After forming the refractory metal silicide 10 on the conductive polysilicon film 9, the first insulating film 7 is formed.
Forming a resist pattern in a range covering the opening 7a of
The first polysilicon film 9 and the refractory metal silicide 10 that have been made conductive are processed to obtain a base extraction electrode. A third insulating film 11 is formed on the base extraction electrode, and an opening 7 a of the first insulating film 7 is formed in the third insulating film 11, the refractory metal silicide 10 and the first polysilicon film 9. An opening slightly smaller inside is formed by continuous RIE or the like. FIG. 2 shows a state immediately after the formation of the opening.

In FIG. 3, the second insulating film 8 exposed again through the opening is etched with an etchant of a hydrogen fluoride (HF) aqueous solution or an ammonium fluoride (NH ₄ F) aqueous solution, so that the collector region 3 is formed. Expose. This etching is performed until the opening end face 7a of the first insulating film 7 is at least partially exposed by side etching. Thereby, a slight eave-shaped space is formed below the first polysilicon film 9. As will be described later, the formation region of the base region is determined by this etching.
Since the etching selectivity by the etchant is high and the side etching does not proceed abruptly from the time when the opening end face 7a of the first insulating film 7 is exposed, the region where the base region is formed is the same as the conventional first insulating film 7 Than without
It is formed accurately and stably.

In FIG. 4, a selective epitaxial method is used.
A base region 12 is grown on the exposed surfaces of the collector region 3 and the first polysilicon film 9. This base region 12
5 × 10 ¹⁷ to 2 × 10 ¹⁹ / c during epitaxial growth
Boron is introduced at a concentration of m ³ to make it conductive. The base region 12 fills the eaves-like space formed by side etching of the second insulating film 8, and the base region 12 is sufficiently electrically connected to the base extraction electrode (the first polysilicon film 9 and the refractory metal silicide 10). Connected.

In FIG. 5, an insulating film such as a silicon oxide film is
About 200 to 1000 nm deposited by CVD or the like,
Etchback is performed from the upper surface of the deposited film by anisotropic etching such as RIE. As a result, a sidewall spacer 13 that separates the emitter and the base is formed.

Thereafter, as shown in FIG. 1, the second polysilicon film 15 which has been made n-type conductive is
The film is formed to a thickness of about nm. Then, an n-type impurity is introduced from the second polysilicon film 15 into the surface portion of the base region 12 by a method such as short-time high-temperature annealing or ELA (Exicimer Laser Annealing) to form an extremely shallow emitter region 14. If the second polysilicon film 15 is patterned into a predetermined shape, the bipolar transistor is completed.

The bipolar transistor described above is not limited to a homojunction type ECL high-speed bipolar transistor, but may be, for example, a SiGe HBT (Heterojunction).
ionBipolar Transistor).

Second Embodiment In this embodiment, the collector region 3 of the first embodiment is replaced with an SIC (Sel).
ectively ion-implanted collector) structure. FIG. 6 is a sectional view showing the structure of the bipolar transistor according to the second embodiment. This bipolar transistor differs from that of the first embodiment in that an SIC region 3 a is formed in the collector region 3. The SIC region 3a is formed so as to extend from the base region 12 to the collector buried region 2 in the deep part of the substrate. The formation of the SIC region 3a is performed, for example, at the stage shown in FIG.
This is achieved by performing ion implantation using the insulating film 8 as a through film and thermally diffusing introduced impurities.

The bipolar transistor of this embodiment is
The kink effect is suppressed by the presence of the SIC region 3a, and the high-speed performance is further improved. SI
The configuration other than the C region 3a and the manufacturing method are the same as those in the first embodiment. In this embodiment, the effects of the present invention such that the dimensional accuracy of the base region 12 is improved can be obtained.

[0028]

As described above, according to the present invention, a high-performance bipolar semiconductor device can be stably manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process of manufacturing the bipolar transistor of FIG. 1 (up to an opening such as a base extraction electrode).

FIG. 3 is a cross-sectional view showing a manufacturing process (side etching of a second insulating film) subsequent to FIG. 2;

FIG. 4 is a sectional view showing a manufacturing process (selective epitaxial growth of a base region) following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing process (formation of a sidewall spacer) subsequent to FIG. 4;

FIG. 6 is a cross-sectional view illustrating a configuration of a bipolar transistor according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method for manufacturing a conventional bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Collector buried area, 3 ... Collector area, 3a ... SIC area in collector area, 4 ... Deep L
OCOS, 5 ... n ⁺ impurity region, 6 ... p ⁺ for element isolation
Impurity region, 7: first insulating film, 8: second insulating film, 9
... first polysilicon film (base extraction electrode layer), 10 ...
Refractory metal silicide (base extraction electrode layer), 11: third insulating film, 12: base region, 13: sidewall spacer, 14: emitter region, 15: second polysilicon film.

Claims (10)

[Claims] 1. An insulating layer having a collector region formed on a front surface side in a semiconductor substrate, an opening formed on the collector region and partially opening a surface of the collector region, and an insulating layer of the insulating layer. Bipolar having an epitaxial layer formed as a base region formed over the entire surface of the collector region portion in the opening, and a base extraction electrode layer connected to a peripheral portion of the epitaxial layer and extending on the upper surface of the insulating layer In the semiconductor device, the insulating layer includes a first insulating film stacked on the collector region and having an opening end face in contact with the epitaxial layer, and a film material having an etching rate higher than that of the first insulating film. And a second insulating film laminated on the first insulating film without contacting the collector region. 2. The bipolar semiconductor device according to claim 1, wherein said first insulating film is made of silicon oxide, and said second insulating film is made of silicon oxide containing impurities. 3. The bipolar semiconductor device according to claim 1, wherein said first insulating film is made of silicon nitride, and said second insulating film is made of silicon oxide. 4. The bipolar semiconductor device according to claim 1, wherein said first insulating film is made of silicon oxynitride, and said second insulating film is made of silicon oxide. 5. The bipolar transistor according to claim 1, wherein the first insulating film is made of an amorphous compound of a group III element and a group V element, and the second insulating film is made of silicon oxide. Type semiconductor device. 6. A collector region is formed on a surface side of a semiconductor substrate, a first insulating film is formed by partially opening a surface of the collector region, and a film having an etching rate higher than that of the first insulating film. A second insulating film made of a material, and a conductive layer serving as a base extraction electrode layer are sequentially laminated, and an outer contour of the conductive layer outside an opening portion of the first insulating film is patterned. The conductive layer covering the opening of the first insulating film is formed with a slightly smaller opening inside the opening of the first insulating film, and the second insulating film is formed through the opening of the conductive layer. When the collector region is exposed by isotropically etching, the opening end surface of the first insulating film is at least partially exposed below the end of the conductive layer, and the exposed surface of the collector region is exposed. , Below the end of the conductive layer A method of manufacturing a bipolar semiconductor device, wherein a base region connected to the conductive layer is formed by filling the space by an epitaxial growth method. 7. The method for manufacturing a bipolar semiconductor device according to claim 6, wherein said first insulating film is made of silicon oxide, and said second insulating film is made of silicon oxide containing impurities. 8. The method for manufacturing a bipolar semiconductor device according to claim 6, wherein said first insulating film is made of silicon nitride, and said second insulating film is made of silicon oxide. 9. The method for manufacturing a bipolar semiconductor device according to claim 6, wherein said first insulating film is made of silicon oxynitride, and said second insulating film is made of silicon oxide. 10. The bipolar transistor according to claim 6, wherein the first insulating film is made of an amorphous compound of a group III element and a group V element, and the second insulating film is made of silicon oxide. Of manufacturing a semiconductor device.