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JPH0234179B2 - - Google Patents

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Publication number
JPH0234179B2
JPH0234179B2 JP56147751A JP14775181A JPH0234179B2 JP H0234179 B2 JPH0234179 B2 JP H0234179B2 JP 56147751 A JP56147751 A JP 56147751A JP 14775181 A JP14775181 A JP 14775181A JP H0234179 B2 JPH0234179 B2 JP H0234179B2
Authority
JP
Japan
Prior art keywords
groove
film
polycrystalline silicon
oxidation
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56147751A
Other languages
Japanese (ja)
Other versions
JPS5850752A (en
Inventor
Toshihiko Fukuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14775181A priority Critical patent/JPS5850752A/en
Publication of JPS5850752A publication Critical patent/JPS5850752A/en
Publication of JPH0234179B2 publication Critical patent/JPH0234179B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Local Oxidation Of Silicon (AREA)

Description

【発明の詳細な説明】 本発明は、半導体装置より詳細に述べるなら
ば、VIP(V−groove Isolation Polycrystal
backfill)絶縁層分離構造を利用して半導体基板
アースをとつた半導体装置の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION To describe the present invention in more detail than a semiconductor device, the present invention relates to a VIP (V-groove Isolation Polycrystal
This invention relates to a method of manufacturing a semiconductor device in which a semiconductor substrate is grounded using an insulating layer separation structure (backfill).

半導体基板(シリコンウエハ)上にエピタキシ
ヤル成長層を形成し、このエピタキシヤル成長層
内にトランジスタなどの能動素子および抵抗など
の受動素子を形成する際にはこれら素子をアイソ
レーシヨン(分離)する必要があり、また適切な
位置にて基板にアースをとるための導体部分をエ
ピタキシヤル成長層に設ける必要がある。アイソ
レーシヨンをPN接合分離方式で行なうならば、
基板まで達する不純物拡散領域を分離層と同時に
アースをとるための導体部分とすることができ
る。半導体基板がP型であればN型のエピタキシ
ヤル成長層にP型不純物(例えばボロン)を分離
拡散するわけであるが、この分離拡散にはかなり
の高温で長時間の熱処理を施こす必要がある。例
えば、2.4μm厚さのエピタキシヤル成長層にボロ
ン(B)を基板に達するまで拡散するには1150〔℃〕
で40分かかる。この熱処理のために半導体装置に
形成される埋込層(buried layer、例えばN+
設領域)からN型不純物も拡散して埋込層がエピ
タキシヤル層内へ拡大し、また、結晶欠陥が誘起
される。このために半導体装置の特性が劣化す
る。
An epitaxial growth layer is formed on a semiconductor substrate (silicon wafer), and when active elements such as transistors and passive elements such as resistors are formed within this epitaxial growth layer, these elements are isolated. It is also necessary to provide a conductive portion in the epitaxial layer for grounding the substrate at an appropriate location. If isolation is performed using the PN junction separation method,
The impurity diffusion region reaching the substrate can be used as a conductor portion for grounding at the same time as the separation layer. If the semiconductor substrate is P-type, P-type impurities (for example, boron) are separated and diffused into the N-type epitaxial growth layer, but this separation and diffusion requires heat treatment at a fairly high temperature for a long time. be. For example, to diffuse boron (B) into a 2.4 μm thick epitaxial growth layer until it reaches the substrate, the temperature is 1150 [℃].
It takes 40 minutes. Due to this heat treatment, N-type impurities are also diffused from the buried layer (for example, N + buried region) formed in the semiconductor device, and the buried layer expands into the epitaxial layer, which also induces crystal defects. be done. This deteriorates the characteristics of the semiconductor device.

VIP構造の絶縁層分離を利用した半導体装置で
は、第1図から明らかなように二酸化シリコン
(SiO2)膜の絶縁膜のために基板とアースをとる
のにVIP構造は使えない。なお、第1図は半導体
装置のVIP構造部分の概略断面図であつて、半導
体基板1とその上のエピタキシヤル成長層2に形
成されたV溝3がV溝表面上の酸化膜(SiO2膜)
4および多結晶(ポリ)シリコン層5によつて満
たされ、そして多結晶シリコン膜5の表面上に厚
い酸化膜(SiO2膜)6がある。
In a semiconductor device using the insulation layer separation of the VIP structure, as is clear from FIG. 1, the VIP structure cannot be used to connect the substrate to ground because of the silicon dioxide (SiO 2 ) insulation film. Note that FIG. 1 is a schematic cross-sectional view of a VIP structure portion of a semiconductor device, and shows that a V-groove 3 formed in a semiconductor substrate 1 and an epitaxial growth layer 2 thereon is an oxide film (SiO 2 ) on the surface of the V-groove. film)
4 and a polycrystalline silicon layer 5, and there is a thick oxide film (SiO 2 film) 6 on the surface of the polycrystalline silicon film 5.

本発明の目的は、PN接合分離での分離拡散の
ような長時間の高温熱処理をしないで半導体装置
の表面から半導体基板にアースをとることのでき
る半導体装置の製造方法を提供することである。
An object of the present invention is to provide a method for manufacturing a semiconductor device that can connect the surface of the semiconductor device to the semiconductor substrate without performing long-term high-temperature heat treatment such as separation diffusion in PN junction separation.

本発明の目的は、VIP絶縁層分離構造を半導体
基板アースに利用した半導体装置の製造方法を提
供することである。
An object of the present invention is to provide a method for manufacturing a semiconductor device using a VIP insulating layer isolation structure for grounding a semiconductor substrate.

上述の目的が、一導電型半導体基板上に反対導
電型エピタキシヤル層を形成する工程と、次いで
前記エピタキシヤル層表面から前記半導体基板に
達するV溝を形成する工程と、次いで、前記V溝
内に、耐酸化膜および多結晶シリコン膜とを順次
堆積する工程と、次いで、前記V溝の先端におけ
る多結晶シリコン膜部分以外の前記多結晶シリコ
ン膜部分を酸化する工程と、次いで、前記酸化さ
れた多結晶シリコン膜を除去し、前記V溝の先端
における多結晶シリコン膜部分を表出する工程
と、次いで前記表出した多結晶シリコン膜部分を
マスクとして前記耐酸化膜を選択的にエツチング
し、前記V溝に先端にのみ耐酸化膜部分を残す工
程と、前記V溝の先端における耐酸化膜部分をマ
スクとして選択酸化を行ない、前記V溝の内面に
酸化シリコン膜を成形する工程と、次いで、前記
耐酸化膜を除去して前記V溝の底部に前記半導体
基板を露出させた後、一導電型不純物を含む半導
体層を前記V溝内に埋設する工程と、次いで、熱
処理を行なつて前記半導体層中の不純物を前記半
導体基板へ拡散する工程とを、有することを特徴
とする半導体装置の製造方法によつて達成するこ
とができる。
The above purpose is to form an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, then to form a V-groove reaching from the surface of the epitaxial layer to the semiconductor substrate, and then to form an epitaxial layer in the V-groove. a step of sequentially depositing an oxidation-resistant film and a polycrystalline silicon film; then a step of oxidizing the polycrystalline silicon film portion other than the polycrystalline silicon film portion at the tip of the V-groove; removing the polycrystalline silicon film and exposing the polycrystalline silicon film at the tip of the V-groove, and then selectively etching the oxidation-resistant film using the exposed polycrystalline silicon film as a mask. a step of leaving an oxidation-resistant film portion only at the tip of the V-groove; a step of performing selective oxidation using the oxidation-resistant film portion at the tip of the V-groove as a mask to form a silicon oxide film on the inner surface of the V-groove; Next, after removing the oxidation-resistant film to expose the semiconductor substrate at the bottom of the V-groove, a step of embedding a semiconductor layer containing one conductivity type impurity in the V-groove is performed, and then heat treatment is performed. This can be achieved by a method for manufacturing a semiconductor device, comprising the step of diffusing impurities in the semiconductor layer into the semiconductor substrate.

V溝形成後から一導電型不純物を含む半導体層
を配設する前までを詳しく述べると、例えば、次
のような工程(ア)〜(キ): (ア) エピタキシヤル成長層および半導体基板の
V溝露出表面を熱酸化によつて薄い二酸化シリ
コン(SiO2)膜を形成する、 (イ) 形成したSiO2膜の上に耐酸化膜である窒化
膜を形成する、 (ウ) この窒化膜の上に多結晶シリコン膜(例え
ば2000Å厚)を薄く形成し、熱酸化によつてこ
の多結晶シリコン膜をV溝先端部を除いて酸化
してSiO2膜を形成する、 (エ) SiO2膜を除去し、酸化されなかつた多結晶
シリコン膜を残す、 (オ) V溝先端部に残つている多結晶シリコン膜
をマスクとしてV溝斜面上の窒化膜を除去す
る、 (カ) 熱酸化によつてV溝斜面をさらに酸化して
SiO2膜を厚くする、および (キ) 残つている多結晶シリコン膜、窒化膜およ
びその下の薄いSiO2膜を除去する、 で行なうことができる。
To describe in detail the process from after V-groove formation to before disposing a semiconductor layer containing one conductivity type impurity, for example, the following steps (a) to (g): (a) Epitaxial growth layer and semiconductor substrate A thin silicon dioxide (SiO 2 ) film is formed on the exposed surface of the V-groove by thermal oxidation. (a) A nitride film, which is an oxidation-resistant film, is formed on the formed SiO 2 film. (c) This nitride film A thin polycrystalline silicon film (e.g., 2000 Å thick) is formed on top of the V-groove, and this polycrystalline silicon film is oxidized by thermal oxidation except for the tip of the V-groove to form a SiO 2 film. (d) SiO 2 (e) Remove the nitride film on the slope of the V-groove using the polycrystalline silicon film remaining at the tip of the V-groove as a mask; (f) Thermal oxidation Further oxidize the V-groove slope by
This can be done by increasing the thickness of the SiO 2 film, and (g) removing the remaining polycrystalline silicon film, nitride film, and thin SiO 2 film thereunder.

以下、本発明に係る半導体基板およびその製造
方法を添付図面を参照して詳細に説明する。
Hereinafter, a semiconductor substrate and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

例えばP型のシリコン半導体基板11(第2
図)の上にN型のシリコンエピタキシヤル成長膜
(例えば厚さ2.4μm)12を形成し、このエピタ
キシヤル成長層の表面に熱酸化法又はCVD
(Chemical Vapour Deposition)法によつて二
酸化シリコン(SiO2)膜13(例えば厚さ1500
Å)、続いてCVD法によつて窒化シリコン
(Si3N4)膜14(例えば厚さ2800Å)を形成す
る。次にホトエツチング法によつてV溝形成領域
の窒化シリコン膜4および二酸化シリコン膜13
を選択エツチングし、さらに異方性エツチングに
よつてエピタキシヤル成長層12および基板11
に第2図に示したようにV溝を形成する。熱酸化
法によつてV溝の表面(斜面)を酸化して薄い二
酸化シリコン膜15(例えば厚さ500Å)を形成
する(第2図)。
For example, P-type silicon semiconductor substrate 11 (second
An N-type silicon epitaxial growth film (for example, 2.4 μm thick) 12 is formed on the top of the epitaxial growth layer (Fig.), and the surface of this epitaxial growth layer is subjected to a thermal oxidation method or
A silicon dioxide (SiO 2 ) film 13 (for example, 1500 mm thick) is deposited by the (Chemical Vapor Deposition) method.
), and then a silicon nitride (Si 3 N 4 ) film 14 (eg, 2800 Å thick) is formed by CVD. Next, the silicon nitride film 4 and silicon dioxide film 13 in the V-groove formation region are etched by photoetching.
The epitaxial growth layer 12 and the substrate 11 are selectively etched and further anisotropically etched.
A V-groove is formed as shown in FIG. The surface (slope) of the V-groove is oxidized by thermal oxidation to form a thin silicon dioxide film 15 (eg, 500 Å thick) (FIG. 2).

CVD法によつて窒化シリコン膜16(例えば
厚さ800Å)をV溝内の二酸化シリコン膜15お
よび先に形成した窒化シリコン膜14の上に堆積
形成する(第3図)。V溝の外の窒化膜14は合
計厚さ(3600Å)となる。続いて、CVD法によ
つて多結晶シリコン膜(例えば厚さ2000Å)を窒
化シリコン膜上に形成し、この多結晶シリコン膜
を熱酸化によつて酸化して二酸化シリコン膜17
(厚さ4000Å)を形成する。この熱酸化の際にV
溝先端部分の多結晶シリコン膜18は酸化されず
に第3図に示すように残る。
A silicon nitride film 16 (eg, 800 Å thick) is deposited by CVD on the silicon dioxide film 15 in the V-groove and the previously formed silicon nitride film 14 (FIG. 3). The total thickness of the nitride film 14 outside the V-groove is 3600 Å. Next, a polycrystalline silicon film (for example, 2000 Å thick) is formed on the silicon nitride film by CVD, and this polycrystalline silicon film is oxidized by thermal oxidation to form a silicon dioxide film 17.
(4000 Å thick). During this thermal oxidation, V
The polycrystalline silicon film 18 at the tip of the groove remains as shown in FIG. 3 without being oxidized.

次に、二酸化シリコン膜17をエツチング液
(フツ酸系溶液)にて除去して多結晶シリコン膜
18および窒化シリコン膜が表出する。続いて窒
化シリコン膜16をエツチング液(リン酸沸騰溶
液)にて除去する。このとき残つている多結晶シ
リコン膜18がマスクとなつてV溝先端部に窒化
シリコン膜16の一部が残り、またV溝の外の窒
化膜14はエツチングによつて薄くなり当初の厚
さとなる(第4図)。
Next, the silicon dioxide film 17 is removed using an etching solution (fluoric acid solution) to expose the polycrystalline silicon film 18 and the silicon nitride film. Subsequently, the silicon nitride film 16 is removed using an etching solution (phosphoric acid boiling solution). At this time, the remaining polycrystalline silicon film 18 serves as a mask, and a portion of the silicon nitride film 16 remains at the tip of the V-groove, and the nitride film 14 outside the V-groove is thinned by etching to its original thickness. (Figure 4).

多結晶シリコン膜18を除去し、熱酸化によつ
てV溝表面の薄い二酸化シリコン膜15を通して
エピタキシヤル成長層12および基板11を酸化
して比較的厚い二酸化シリコン膜19(例えば厚
さ5000Å)を形成する(第5図)。
The polycrystalline silicon film 18 is removed, and the epitaxial growth layer 12 and substrate 11 are oxidized by thermal oxidation through the thin silicon dioxide film 15 on the V-groove surface to form a relatively thick silicon dioxide film 19 (for example, 5000 Å thick). form (Figure 5).

V溝の先端に残つている窒化シリコン膜16を
エツチング除去する。このとき、窒化シリコン膜
14も厚さが減少するが除去してはいけない。続
いて、V溝先端にある薄い二酸化シリコン膜15
をエツチング除去して半導体基板11を表出す
る。このエツチングによつてV溝表面の比較的厚
い二酸化シリコン膜19も厚さが約500Åだけ減
少する。次に、CVD法によつて不純物(例えば
ボロン)をドープしながら多結晶シリコンをV溝
を埋める程厚く形成し、ラツピングによつてV溝
内にのみこの多結晶シリコン20を残して他を除
去する(第6図)。もちろん多結晶シリコン成長
後、ラツピングしてから不純物をドープしてもか
まわない。ラツピングの際に窒化シリコン膜14
がストツパとして働く。
The silicon nitride film 16 remaining at the tip of the V-groove is removed by etching. At this time, the thickness of the silicon nitride film 14 is also reduced, but it must not be removed. Next, a thin silicon dioxide film 15 at the tip of the V-groove is
is removed by etching to expose the semiconductor substrate 11. This etching also reduces the thickness of the relatively thick silicon dioxide film 19 on the V-groove surface by about 500 Å. Next, polycrystalline silicon is formed thick enough to fill the V-groove while doping impurities (for example, boron) using the CVD method, and by wrapping, the polycrystalline silicon 20 is left only in the V-groove and the rest is removed. (Figure 6). Of course, impurities may be doped after the polycrystalline silicon is grown and wrapped. During wrapping, the silicon nitride film 14
acts as a stopper.

そして、多結晶シリコン20の表面を熱酸化し
て厚い二酸化シリコン膜21(例えば厚さ8000
Å)を形成する。この熱処理によつて多結晶シリ
コン20内にドープされていた不純物(ボロン)
がV溝先端部で半導体基板11内へ拡散し、また
トランジスタのベース、エミツタなどを形成する
際の熱処理によつても拡散して第7図の破線で示
した領域22へ広がる。この拡散領域22はチヤ
ネルカツトもかねている。表面の二酸化シリコン
膜21にコンタクトのための開孔をホトエツチン
グ法で形成し、アース電極23を形成する。この
ようにして基板にアースをとることができ、本発
明に係る半導体装置が得られる。
Then, the surface of the polycrystalline silicon 20 is thermally oxidized to form a thick silicon dioxide film 21 (for example, 8000 mm thick).
Å) is formed. Impurities (boron) doped into the polycrystalline silicon 20 by this heat treatment
diffuses into the semiconductor substrate 11 at the tip of the V-groove, and also diffuses during heat treatment when forming the base, emitter, etc. of the transistor, and spreads to the region 22 shown by the broken line in FIG. This diffusion region 22 also serves as a channel cut. An opening for contact is formed in the silicon dioxide film 21 on the surface by photoetching, and a ground electrode 23 is formed. In this way, the substrate can be grounded, and a semiconductor device according to the present invention can be obtained.

図面上にはトランジスタ等の能動素子や受動素
子および埋込層を示していないが、通常の公知方
法によつてこれらが形成される。
Although active elements such as transistors, passive elements, and buried layers are not shown in the drawings, they are formed by conventional known methods.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、VIP絶縁層分離構造を有する半導体
装置の部分断面図であり、第2図ないし第7図は
本発明に係る半導体装置の製造方法を説明する半
導体装置の部分断面図である。 11……半導体基板、12……エピタキシヤル
成長層、13……二酸化シリコン膜、14……窒
化シリコン膜、15……二酸化シリコン膜、16
……窒化シリコン膜、18……多結晶シリコン、
19……二酸化シリコン膜、20……多結晶シリ
コン、22……拡散領域、23……アース電極。
FIG. 1 is a partial cross-sectional view of a semiconductor device having a VIP insulation layer isolation structure, and FIGS. 2 to 7 are partial cross-sectional views of the semiconductor device for explaining a method of manufacturing a semiconductor device according to the present invention. 11... Semiconductor substrate, 12... Epitaxial growth layer, 13... Silicon dioxide film, 14... Silicon nitride film, 15... Silicon dioxide film, 16
...Silicon nitride film, 18...Polycrystalline silicon,
19... Silicon dioxide film, 20... Polycrystalline silicon, 22... Diffusion region, 23... Earth electrode.

Claims (1)

【特許請求の範囲】 1 一導電型半導体基板上に反対導電型エピタキ
シヤル層を形成する工程と、 次いで、前記エピタキシヤル層から前記半導体
基板に達するV溝を形成する工程と、 次いで、前記V溝内に、耐酸化膜および多結晶
シリコン膜を順次堆積する工程と、 次いで、前記V溝の先端における多結晶シリコ
ン膜部分以外の前記多結晶シリコン膜部分を酸化
する工程と、 次いで、前記酸化された多結晶シリコン膜を除
去し、前記V溝の先端における多結晶シリコン膜
部分を表出する工程と、 次いで、前記表出した多結晶シリコン膜部分を
マスクとして前記耐酸化膜を選択的にエツチング
し、前記V溝の先端にのみ耐酸化膜部分を残す工
程と、 前記V溝の先端における耐酸化膜部分をマスク
として選択酸化を行ない、前記V溝の内面に酸化
シリコン膜を形成する工程と、 次いで、前記耐酸化膜を除去して前記V溝の底
部に前記半導体基板を露出させた後、一導電型不
純物を含む半導体層を前記V溝内に埋設する工程
と、 次いで、熱処理を行なつて前記半導体層中の不
純物を前記半導体基板へ拡散する工程とを、有す
ることを特徴とする半導体装置の製造方法。
[Scope of Claims] 1. A step of forming an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type; Next, a step of forming a V groove reaching from the epitaxial layer to the semiconductor substrate; a step of sequentially depositing an oxidation-resistant film and a polycrystalline silicon film in the groove; then a step of oxidizing the polycrystalline silicon film portion other than the polycrystalline silicon film portion at the tip of the V-groove; removing the exposed polycrystalline silicon film to expose the polycrystalline silicon film portion at the tip of the V-groove, and then selectively removing the oxidation-resistant film using the exposed polycrystalline silicon film portion as a mask. A step of etching to leave an oxidation-resistant film portion only at the tip of the V-groove, and a step of performing selective oxidation using the oxidation-resistant film portion at the tip of the V-groove as a mask to form a silicon oxide film on the inner surface of the V-groove. Then, after removing the oxidation-resistant film to expose the semiconductor substrate at the bottom of the V-groove, burying a semiconductor layer containing one conductivity type impurity in the V-groove, and then heat treatment. and diffusing impurities in the semiconductor layer into the semiconductor substrate.
JP14775181A 1981-09-21 1981-09-21 Manufacturing method of semiconductor device Granted JPS5850752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14775181A JPS5850752A (en) 1981-09-21 1981-09-21 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14775181A JPS5850752A (en) 1981-09-21 1981-09-21 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5850752A JPS5850752A (en) 1983-03-25
JPH0234179B2 true JPH0234179B2 (en) 1990-08-01

Family

ID=15437317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14775181A Granted JPS5850752A (en) 1981-09-21 1981-09-21 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5850752A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745081A (en) * 1985-10-31 1988-05-17 International Business Machines Corporation Method of trench filling
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
JPS63116445A (en) * 1986-11-04 1988-05-20 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US4835586A (en) * 1987-09-21 1989-05-30 Siliconix Incorporated Dual-gate high density fet

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525501A (en) * 1978-08-04 1980-02-23 Supensaa Hetsuzu Inc Insert for ignition deck of internal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525501A (en) * 1978-08-04 1980-02-23 Supensaa Hetsuzu Inc Insert for ignition deck of internal

Also Published As

Publication number Publication date
JPS5850752A (en) 1983-03-25

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