JPS58223803A - PID controller - Google Patents
PID controllerInfo
- Publication number
- JPS58223803A JPS58223803A JP10686182A JP10686182A JPS58223803A JP S58223803 A JPS58223803 A JP S58223803A JP 10686182 A JP10686182 A JP 10686182A JP 10686182 A JP10686182 A JP 10686182A JP S58223803 A JPS58223803 A JP S58223803A
- Authority
- JP
- Japan
- Prior art keywords
- calculation
- pid
- circuit
- pid controller
- calculation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 210000000988 bone and bone Anatomy 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 102100027581 Forkhead box protein P3 Human genes 0.000 description 1
- 101000861452 Homo sapiens Forkhead box protein P3 Proteins 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B11/00—Automatic controllers
- G05B11/01—Automatic controllers electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はＰＩＤ！！ｌｉｔ節針に係り、特に容易にむだ
時間補償演算やフィードフォワード演算を行うＰＩＤｉ
Ｑ１節計とする０に好適な構造のＰＩＤ調節計に関する
ものである。[Detailed Description of the Invention] The present invention is based on PID! ! PIDi, which is particularly easy to perform dead time compensation calculations and feedforward calculations related to lit point hands.
This invention relates to a PID controller having a structure suitable for 0 with a Q1 meter.
第１図は一般的なＰＩＤ調節計の構成図である。FIG. 1 is a block diagram of a general PID controller.
第１図に示すように、ＰＩＤ調節計は、入力ＩＮと設定
回路１で設定した設定信号との偏差を演算する偏差演算
回路２、偏差演算回路２からの出力をＰＩＤ演算を行う
ＰＩＤ演算回路３およびＰＩＤ演算回路の出力と手動出
力回路４の出力とを必要に応じて切り換えて出力する出
力回路５とより構成しである。As shown in Fig. 1, the PID controller includes a deviation calculation circuit 2 that calculates the deviation between the input IN and the setting signal set by the setting circuit 1, and a PID calculation circuit that performs PID calculation on the output from the deviation calculation circuit 2. 3 and an output circuit 5 which switches and outputs the output of the PID calculation circuit and the output of the manual output circuit 4 as necessary.
第２図はむだ時間補償演算付ＰＩＤ調節計の構成図であ
り、第１図と同一部分は同じ符号で示し、ここでは説明
を省略する。図に示すように、一般的なＰＩＤＩＭＩ節
計にむだ時間補償演算回路６と加減算器７とが付加しで
ある。FIG. 2 is a block diagram of a PID controller with dead time compensation calculation. The same parts as in FIG. As shown in the figure, a dead time compensation calculation circuit 6 and an adder/subtractor 7 are added to the general PIDIMI moderator.
また、フィードフォワード演算性ＰＩＤｖ＠特許罠おい
ては、第３図に示すように１第１図に示す一般的なＰＩ
Ｄ調節計にフィードフォワード演算器８と加減算器９と
が付加しである。In addition, in the feedforward operability PIDv@patent trap, as shown in Fig. 3, 1 general PI shown in Fig. 1 is used.
A feedforward calculator 8 and an adder/subtractor 9 are added to the D controller.
ところで、従来、これらのＰＩＤ調節計は、それぞれ必
要に応じて内部構成を変え、全体が一つに纒まった独立
した計器の形態をとるように製作していた。したがって
、ＰＩＤ調節計は、種類の計器をシリーズとして用意し
ておかなければならなかった。Incidentally, conventionally, these PID controllers have been manufactured in such a way that the internal configuration of each controller is changed as necessary, and the entire controller is integrated into an independent instrument. Therefore, PID controllers had to be prepared as a series of different types of instruments.
本発明は上記に鑑みてなされたもので、その目的とする
ところは、種々の制御に用いる各種のＰＩＤ調節計を各
構成要素の端子間接続によって構成できるＰＩＤ調節計
を提供することにある。The present invention has been made in view of the above, and an object of the present invention is to provide a PID controller that can be used for various types of control by connecting terminals of each component.
本発明の特徴は、偏差演算回路、ＰＩＤ演算回路および
出力回路とをそれぞれ相互に接続可能の接続端子を設け
た独立した構成の゛ものとし、必要に応じて接続端子を
設け゛たむだ時間補償演算回路あるいはフィードフォワ
ード演算器を含めて上記各接続端子間をそれぞれ決めら
ｒｔたように接続し、ｌ−ｒ；’ｌ？ｌｆｉ１ｍｌ：Ｊ
’ＥＨＰ Ｉ ＤＮｉｌ’ｌｉ＋、 ｔｒ；Ｉ’２Ｒｆ
＄Ｊ］補償１算付ＰＩＤ調節計あるいはフィードフォワ
ード演算性ＰＩＤ調節計を構成できるようにした点にあ
る。A feature of the present invention is that the deviation calculation circuit, the PID calculation circuit, and the output circuit are each provided with connection terminals that can be connected to each other and have an independent configuration, and connection terminals are provided as necessary. Connect the above-mentioned connection terminals including the circuit or feedforward computing unit in the determined manner, and l-r;'l? lfi1ml:J
'EHP I DNil'li+, tr;I'2Rf
[$J] It is possible to configure a PID controller with compensation 1 calculation or a PID controller with feedforward operation.
以下本発明を第４図〜第６図に示した実施例を用いて詳
細に説明する。The present invention will be explained in detail below using the embodiments shown in FIGS. 4 to 6.
第４図は本発明のＰＩＤ調節計の一実施例を示す構成図
で、一般的なＰＩＤ調節計を示してあり、第１図と同一
部分は同じ符号で示し、ここでは説明を省略する。第４
図においては、偏差演算回路２、ＰＩＤ演算回路３およ
び出力回路５とがそれぞれ独立した構成としてあり、偏
差演算回路２には接続端子１０を、ＰＩＤ演算回路３に
は接続端子１１．１２を、出力回路５には接続端子１３
を設け、端子１０と１１．１２と１３を外部接続するこ
とにより、第１図に示す一般的なｐ ＩＤ調節計として
動作させることができるように構成してるる。FIG. 4 is a block diagram showing an embodiment of the PID controller of the present invention, and shows a general PID controller. The same parts as in FIG. Fourth
In the figure, the deviation calculation circuit 2, the PID calculation circuit 3, and the output circuit 5 are each configured independently, and the deviation calculation circuit 2 has a connection terminal 10, the PID calculation circuit 3 has a connection terminal 11.12, The output circuit 5 has a connection terminal 13
By connecting terminals 10, 11, 12, and 13 externally, the controller is constructed so that it can be operated as a general PID controller shown in FIG.
第５図は本発明の他の実施例を示す第２図と同様のむだ
時間補償演算付ＰｒＤ調節計の構成図で、第４図と同一
部分は同じ符号で示しである。第５図においては、むだ
時間補償演算回路６と加減算器７とを一つのユニットと
して構成し、これに図示のように接続端子１４〜１５を
設けておき、端子１０と１４．１１と１５および１２．
１３と１６とをそｉｔぞれ外部接続して第２図と同様の
むだ時間補償演算骨ＰＩＤＸ特許としである。FIG. 5 is a block diagram of a PrD controller with dead time compensation calculation similar to FIG. 2 showing another embodiment of the present invention, and the same parts as in FIG. 4 are designated by the same reference numerals. In FIG. 5, the dead time compensation arithmetic circuit 6 and the adder/subtractor 7 are configured as one unit, and connection terminals 14 to 15 are provided as shown in the figure. 12.
13 and 16 are each connected externally to obtain a dead time compensation calculation bone PIDX patent similar to that shown in FIG.
第６図は本発明のさらに他の実施例を示す第３図と同様
のフィードフォワード演算性ＰＩＤ調節計の構成図で、
第４図と同一部分は同じ符号で示しである。第６図にお
いては、フィードフォワード演算器８と加減算器９とを
一つのユニットとして構成し、これに図示のように接続
端子１７゜１８を設けておき、端子１０と１１．１２と
１７および１３と１８とをそれぞれ外部接続して第３図
と同様のフィードフォワード演算付ＰＩＤ調節針としで
ある。FIG. 6 is a block diagram of a feedforward operation PID controller similar to FIG. 3 showing still another embodiment of the present invention.
The same parts as in FIG. 4 are indicated by the same reference numerals. In FIG. 6, the feedforward calculator 8 and the adder/subtractor 9 are configured as one unit, and connection terminals 17 and 18 are provided as shown in the figure, and the terminals 10, 11, 12, 17, and 13 are connected to each other. and 18 are connected externally to form a PID adjustment needle with feedforward calculation similar to that shown in FIG.
上記した各実施例においては、それぞれ接続端子を設け
た偏差演算回路二二ツ）、ＰＩＤ演算回路ユニット、出
力回路ユニットよりなる構成としであるので、各接続端
子間をあらかじめ決められたよう忙接続することによっ
て一般的なＰＩＤ調節計とすることができ、また、別に
接続端子を設けたむだ時間補償演算回路ユニットを用意
して、各接続端子間をあらかじめ決められたように接続
することによってむだ時間補償演算材ＰＩＤ調節計とす
ることもでき、さらに、接続端子を設けたフィードフォ
ワード演算器二二ッＩｆ用意して、各接続端子間ｔ−あ
らかじめ決められたように接続することによってフィー
ドフォワード演算付ＰＩＤｐ４特許とすることもできる
。In each of the above-mentioned embodiments, the configuration is made up of a deviation calculation circuit (22), a PID calculation circuit unit, and an output circuit unit each having a connection terminal, so that the connection terminals are connected in a predetermined manner. By doing this, it can be used as a general PID controller, and by preparing a dead time compensation calculation circuit unit with separate connection terminals and connecting each connection terminal in a predetermined manner, waste time can be reduced. It is also possible to use a time-compensated calculation element PID controller.Furthermore, a feedforward calculation unit (2If) provided with connection terminals is prepared, and the feedforward operation is performed by connecting each connection terminal in a predetermined manner. It can also be a PIDp4 patent with calculation.
以上説明したように、本発明によれば、種々の制御に用
いる各種のＰＩＤ調節計を各構成要素の端子間接続によ
って構成できるという効果がある。As described above, the present invention has the advantage that various PID controllers used for various controls can be constructed by connecting terminals of each component.
【図面の簡単な説明】
第１図、第２図、第３図はそれぞれ従来の一般的なＰＩ
Ｄ調節針、むだ時間補償演算材ＰＩＤ調節計、フィード
フォワード演算付ＰＩＤＩ！Ｍ１特許の構成図、第４図
、第５図、第６図はそれぞれ本発明のＰＩＤ調節計の一
実施例を示す構成図で、第４図は一般的なＰＩＤ調節計
、第５図はむだ時間補償演算付ＰＩＤ調節針、第６図は
フィードフォワード演算性ＰＩＤ調節計の構成図である
。
１・・・設定回路、２・・・偏差演算回路、３・・・Ｐ
ＩＤ演算回路、４・・・手動出力回路、５・・・出力回
路、６・・・むだ時間補償演算回路、７．９・・・加減
算器、８・・・フィードフォワード演算器、１０〜１８
・・・接続端差ｌ目
茅２ 口
茅Ｊ り
茅４ 囚
＄５ 口[Brief explanation of the drawings] Figures 1, 2, and 3 are conventional general PIs, respectively.
D adjustment needle, dead time compensation calculation material PID controller, PIDI with feedforward calculation! The block diagrams of the M1 patent, FIGS. 4, 5, and 6 are block diagrams showing one embodiment of the PID controller of the present invention, respectively. FIG. 4 is a general PID controller, and FIG. FIG. 6 is a block diagram of a PID controller with dead time compensation calculation. 1... Setting circuit, 2... Deviation calculation circuit, 3... P
ID arithmetic circuit, 4... Manual output circuit, 5... Output circuit, 6... Dead time compensation arithmetic circuit, 7.9... Adder/subtractor, 8... Feedforward arithmetic unit, 10 to 18
・・・Connection end difference 1 eyes 2 eyes 2 eyes 4 eyes 5 mouth
Claims (1)
偏差演算回路と、該偏差演算回路からの出力をＰＩＤ演
算を行うＰＩＤ演算回路と、該ＰＩＤ演算回路の出力と
手動出力回路の出力とを必要に応じて切り換えて出力す
る出力回路とを備えたＰＩＤ調節計において、前記偏差
演算回路、ＰＩＤ演算回路および出力回路とをそれぞれ
相互に接続可能の端子を設けた独立した構成のものとし
、必要に応じて接続端子を設けたむだ時間補償演算回路
あるいはフィードフォワード演算器を含めて前記各接続
端子間をそれぞれ決められたように接続して不感帯演算
骨ＰＩＤ調節計、むだ時間補償演算付ＰＩＤ調節計ある
いはフィードフォワード演算骨ＰＩＤ調節計を構成でき
るようにしであることを特徴とするＰＩＤ調節計。1. A deviation calculation circuit that calculates the deviation between the input and the setting signal from the setting circuit, a PID calculation circuit that performs PID calculation on the output from the deviation calculation circuit, and the output of the PID calculation circuit and the output of the manual output circuit. In the PID controller, the deviation calculation circuit, the PID calculation circuit, and the output circuit each have an independent configuration with terminals that can be connected to each other. , including a dead time compensation calculation circuit or a feedforward calculation unit provided with connection terminals as necessary, and connecting the connection terminals in a predetermined manner to perform dead zone calculation bone PID controller with dead time compensation calculation. A PID controller, characterized in that it can be configured as a PID controller or a feedforward calculation bone PID controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10686182A JPS58223803A (en) | 1982-06-23 | 1982-06-23 | PID controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10686182A JPS58223803A (en) | 1982-06-23 | 1982-06-23 | PID controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58223803A true JPS58223803A (en) | 1983-12-26 |
Family
ID=14444345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10686182A Pending JPS58223803A (en) | 1982-06-23 | 1982-06-23 | PID controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58223803A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524714A (en) * | 2007-04-23 | 2010-07-22 | 本田技研工業株式会社 | Method for controlling joint and torque speed converter |
-
1982
- 1982-06-23 JP JP10686182A patent/JPS58223803A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524714A (en) * | 2007-04-23 | 2010-07-22 | 本田技研工業株式会社 | Method for controlling joint and torque speed converter |
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