JPS63275220A - Multiplication circuit - Google Patents
Multiplication circuitInfo
- Publication number
- JPS63275220A JPS63275220A JP62111247A JP11124787A JPS63275220A JP S63275220 A JPS63275220 A JP S63275220A JP 62111247 A JP62111247 A JP 62111247A JP 11124787 A JP11124787 A JP 11124787A JP S63275220 A JPS63275220 A JP S63275220A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- waveform
- capacitor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、逓倍回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplier circuit.
従来、逓倍回路には、排他的論理和回路（以下ＥＸ−Ｏ
Ｒという〉と遅延回路とを使用した第３図に示す回路が
使われている。第４図は第３図に示す従来例のタイミン
グチャートである。入力端子１０３に入力信号Ｊを入力
すると、遅延回路１０１により、信号ＫがＥＸ−ＯＲ１
０２に入力される。ＥＸ−ＯＲ１０２により入力信号Ｊ
と信号にとの排他的論理和を取ることにより、出力端子
１０４に出力波形りが得られ、逓倍動作を行う。Conventionally, an exclusive OR circuit (hereinafter EX-O) is used as a multiplier circuit.
A circuit shown in FIG. 3 using a delay circuit and a delay circuit is used. FIG. 4 is a timing chart of the conventional example shown in FIG. When input signal J is input to input terminal 103, signal K is output to EX-OR1 by delay circuit 101.
02 is input. Input signal J by EX-OR102
By taking the exclusive OR of the signal and the signal, an output waveform is obtained at the output terminal 104, and a multiplication operation is performed.
上述した従来の逓倍回路は、ある決まった遅延時間をも
った遅延回路により入力信号を遅らせ、入力信号と排他
的論理和をとるため、出力信号が方形波であり、立ち上
り時間、立ち下り時間が同じである逓倍された三角波を
得ることができないという欠点がある。The conventional multiplier circuit described above delays the input signal using a delay circuit with a certain fixed delay time and performs an exclusive OR with the input signal, so the output signal is a square wave and the rise time and fall time are The disadvantage is that it is not possible to obtain the same multiplied triangular wave.
本発明の逓倍回路は、第一の電圧制御電流源の出力に第
一のコンデンサの一端を接続し、この第一のコンデンサ
の他端を接地し、この第一のコンデンサの両端に第一の
電圧制御スイッチの接点を接続し、第二の電圧制御電流
源の出力に第二のコンデンサの一端を接続し、この第二
のコンデンサの他端を接地し、この第二のコンデンサの
両端に第二の電圧制御スイッチの接点を接続し、入力信
号は前記第一の電圧制御スイッチの制御端子および否定
回路の入力に接続し、この否定回路の出力は前記第二の
電圧制御スイッチの制御端子に接続し、前記第一の電圧
制御電流源の出力および前記第二の電圧制御電流源の出
力は加算回路で加算し、その加算出力を平滑回路の入力
およびハイパスフィルタの入力に接続し、前記平滑回路
の出力は演算増幅器の反転入力端子に接続し、この・演
算増幅器の非反転入力端子は基準電圧源に接続し、前記
演算増幅器の出力は前記第一の電圧制御電流源の制御端
子および前記第二の電圧制御電流源の制御端子に接続し
、前記ハイパスフィルタの出力は全波整流回路に接続し
、この全波整流回路の出力を逓倍出力とする構成からな
る。The multiplier circuit of the present invention connects one end of a first capacitor to the output of a first voltage-controlled current source, grounds the other end of this first capacitor, and connects a first capacitor to both ends of this first capacitor. Connect the contacts of the voltage-controlled switch, connect one end of a second capacitor to the output of the second voltage-controlled current source, ground the other end of this second capacitor, and connect a second capacitor across both ends of this second capacitor. The contacts of the second voltage-controlled switch are connected, and the input signal is connected to the control terminal of the first voltage-controlled switch and the input of a negative circuit, and the output of this negative circuit is connected to the control terminal of the second voltage-controlled switch. The output of the first voltage-controlled current source and the output of the second voltage-controlled current source are added in an adder circuit, and the added output is connected to the input of the smoothing circuit and the input of the high-pass filter. The output of the circuit is connected to the inverting input terminal of an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to a reference voltage source, and the output of the operational amplifier is connected to the control terminal of the first voltage-controlled current source and the The high-pass filter is connected to a control terminal of a second voltage-controlled current source, the output of the high-pass filter is connected to a full-wave rectifier circuit, and the output of the full-wave rectifier circuit is multiplied.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示す実施例のタイミングチャートである。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart of the embodiment shown in FIG.
入力端子１５から入力する入力信号Ａは、第一の電圧制
御電流源１と、第一のコンデンサ２と、ＮＰＮ）ランジ
スタによる第一の電圧制御スイッチ３とにより波形Ｂを
得る。同時に入力信号Ａは、否定回路４と、第二の電圧
制御電流源５と、第二のコンデンサ６と、ＮＰＮ トラ
ンジスタによる第二の電圧制御スイッチ７とにより波形
Ｃを得る。An input signal A input from an input terminal 15 obtains a waveform B by a first voltage-controlled current source 1, a first capacitor 2, and a first voltage-controlled switch 3 formed by an NPN transistor. At the same time, the input signal A obtains a waveform C by the inverter 4, the second voltage-controlled current source 5, the second capacitor 6, and the second voltage-controlled switch 7 formed by an NPN transistor.
波形Ｂと波形Ｃとは、加算回路８により、のこぎり波形
りを得る。のこぎり波形りは、平滑回路９により平均電
圧Ｆに変換される。基準電圧源１０の電圧と平均電圧Ｆ
とが同じになる様に、演算増幅器１１は第一の電圧制御
電流源１および第二の電圧制御電流源５を制御する。ま
た、のこぎり波形りは、ハイパスフィルタ１２により直
流電圧分を除去し、平均電圧Ｆを電圧０とする波形とな
る。Waveform B and waveform C are converted into sawtooth waveforms by an adder circuit 8. The sawtooth waveform is converted into an average voltage F by a smoothing circuit 9. Voltage of reference voltage source 10 and average voltage F
The operational amplifier 11 controls the first voltage-controlled current source 1 and the second voltage-controlled current source 5 so that the values are the same. Further, the sawtooth waveform becomes a waveform in which the DC voltage component is removed by the high-pass filter 12, and the average voltage F becomes zero voltage.
この波形を全波整流回路１３により全波整流し、出力波
形Ｅを出力端子１４から得る。This waveform is full-wave rectified by a full-wave rectifier circuit 13, and an output waveform E is obtained from an output terminal 14.
以上説明したように本発明は、のこぎり波の平均電圧と
基準電圧とを比較することにより電圧制御電流源とコン
デンサとによる積分回路の積分量を制御しているので、
どの様な入力周波数でも逓倍された三角波が得られる効
果がある。As explained above, the present invention controls the amount of integration of the integrating circuit formed by the voltage-controlled current source and the capacitor by comparing the average voltage of the sawtooth wave with the reference voltage.
The effect is that a multiplied triangular wave can be obtained at any input frequency.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示す実施例のタイミングチャート、第３図は従
来の逓倍回路の一例のブロック図、第４図は第３図に示
す従来例のタイミングチャートである。
１・・・第一の電圧制御電流源、２・・・第一のコンデ
ンサ、３・・・第一の電圧制御スイッチ、４・・・否定
回路、５・・・第二の電圧制御電流源、６・・・第二の
コンデンサ、７・・・第二の電圧制御スイッチ、８・・
・加算回路、９・・・平滑回路、１０・・・基準電圧源
、１１・・・演算増幅器、１２・・・ハイパスフィルタ
、１３・・・全波整流回路、１４・・・出力端子、１５
・・・入力端子。
茅 ！ 凹
茅 ３ 菌
稟 ４ 図FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of the embodiment shown in FIG. 1, FIG. 3 is a block diagram of an example of a conventional multiplier circuit, and FIG. 3 is a timing chart of the conventional example shown in the figure. DESCRIPTION OF SYMBOLS 1... First voltage controlled current source, 2... First capacitor, 3... First voltage controlled switch, 4... Inverting circuit, 5... Second voltage controlled current source , 6... second capacitor, 7... second voltage control switch, 8...
- Adding circuit, 9... Smoothing circuit, 10... Reference voltage source, 11... Operational amplifier, 12... High pass filter, 13... Full wave rectifier circuit, 14... Output terminal, 15
...Input terminal. Kaya! Concave grass 3 Fungi 4 Diagram
Claims (1)
を接続し、この第一のコンデンサの他端を接地し、この
第一のコンデンサの両端に第一の電圧制御スイッチの接
点を接続し、第二の電圧制御電流源の出力に第二のコン
デンサの一端を接続し、この第二のコンデンサの他端を
接地し、この第二のコンデンサの両端に第二の電圧制御
スイッチの接点を接続し、入力信号は前記第一の電圧制
御スイッチの制御端子および否定回路の入力に接続し、
この否定回路の出力は前記第二の電圧制御スイッチの制
御端子に接続し、前記第一の電圧制御電流源の出力およ
び前記第二の電圧制御電流源の出力は加算回路で加算し
、その加算出力を平滑回路の入力およびハイパスフィル
タの入力に接続し、前記平滑回路の出力は演算増幅器の
反転入力端子に接続し、この演算増幅器の非反転入力端
子は基準電圧源に接続し、前記演算増幅器の出力は前記
第一の電圧制御電流源の制御端子および前記第二の電圧
制御電流源の制御端子に接続し、前記ハイパスフィルタ
の出力は全波整流回路に接続し、この全波整流回路の出
力を逓倍出力とすることを特徴とする逓倍回路。Connect one end of the first capacitor to the output of the first voltage-controlled current source, ground the other end of this first capacitor, and connect the contacts of the first voltage-controlled switch to both ends of this first capacitor. Connect one end of a second capacitor to the output of the second voltage-controlled current source, ground the other end of this second capacitor, and connect the contacts of a second voltage-controlled switch to both ends of this second capacitor. and the input signal is connected to the control terminal of the first voltage control switch and the input of the inverting circuit,
The output of this inverting circuit is connected to the control terminal of the second voltage-controlled switch, and the output of the first voltage-controlled current source and the output of the second voltage-controlled current source are added by an adder circuit, and the sum is an output connected to an input of a smoothing circuit and an input of a high-pass filter; the output of the smoothing circuit is connected to an inverting input terminal of an operational amplifier; a non-inverting input terminal of the operational amplifier is connected to a reference voltage source; The output of the high-pass filter is connected to the control terminal of the first voltage-controlled current source and the control terminal of the second voltage-controlled current source, and the output of the high-pass filter is connected to a full-wave rectifier circuit. A multiplier circuit characterized in that the output is multiplied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111247A JPS63275220A (en) | 1987-05-06 | 1987-05-06 | Multiplication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111247A JPS63275220A (en) | 1987-05-06 | 1987-05-06 | Multiplication circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63275220A true JPS63275220A (en) | 1988-11-11 |
Family
ID=14556325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111247A Pending JPS63275220A (en) | 1987-05-06 | 1987-05-06 | Multiplication circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63275220A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007058217A1 (en) * | 2005-11-16 | 2007-05-24 | Rohm Co., Ltd. | Triangular-wave generating circuit, and inverter, light emitting device and liquid crystal television using the circuit |
| JP2015187434A (en) * | 2014-03-27 | 2015-10-29 | ダイハツ工業株式会社 | Internal combustion engine |
-
1987
- 1987-05-06 JP JP62111247A patent/JPS63275220A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007058217A1 (en) * | 2005-11-16 | 2007-05-24 | Rohm Co., Ltd. | Triangular-wave generating circuit, and inverter, light emitting device and liquid crystal television using the circuit |
| US7948282B2 (en) | 2005-11-16 | 2011-05-24 | Rohm Co., Ltd. | Triangular-wave generating circuit, and inverter, light emitting device and liquid crystal television using the circuit |
| JP2015187434A (en) * | 2014-03-27 | 2015-10-29 | ダイハツ工業株式会社 | Internal combustion engine |
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