JPS58215169A - Method and device for binary coding picture signal - Google Patents

Abstract

PURPOSE:To obtain a binary-coded signal within a short arithmetic processing time, by finding an error of a binary-coded luminance value of an already determined picture element of the peripheral of an aimed picture element with respect to a correction luminance value, and finding a correction luminance value of the aimed picture element by multiplying said error by a specified weight coefficient in order to compare the correction luminance value with a threshold. CONSTITUTION:A coefficient which can be expressed in the form of 2-N (N: natural number) is used as a weight coefficient of an average error minimum method. An analog picture signal which is an input read by a CCD, etc., is performed digital conversion 1 and subtraction processing 2 and inputted in an adder 3. Initially, (a), (b) and (c) are set to zeros, and a luminance value J1,1 related to the first picture element (1,1) is added with nothing and inputted in a latch 19. Thereafter, the J1,1 is latched to the latch 19 and inputted in an adder 4, and simultaneously a J2,1 is inputted in the adder 3. In the same manner, the J1,1 is continuously shifted and supplied to a comparator 17 out of a latch 28. An I1,1 is found, and an E1,1 is calculated. The E1,1 is led to an arithmetic processing part 18 to be supplied to ech adder. As it is clear from the numbers of adders 3-7 and 9-16 and stage numbers of shift registers 8 and 14, numbers of error addition is gradually increased, and the comparator 17 outputs a binary-coded signal IX,Y corresponding to the negative/positive of a J'X,Y.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binarization method and a binarization device for both signals using the minimum average error method. The value of the binarized brightness value (calculate the error that weighs against the brightness value, multiply the error by a predetermined coefficient), and adjust this to the actual brightness value of the pixel of interest to obtain the value of the pixel of interest. The present invention relates to a method and device for binarizing an image signal, characterized in that a corrected luminance value is obtained and a binarized signal is obtained by comparing the corrected luminance value with a threshold value.

According to the dither method, halftones can be substantially expressed at two levels, black and white.Recently, this method has attracted attention and is beginning to be adopted in facsimiles and the like. There are two types of Iser methods: the systematic daily method and the random dither method.Due to the intermediate nature of the hardware configuration, the systematic daily method is used, and the latter random dither method is unique. It is hardly used.

By the way, in the image transmission system 71\, pixel density conversion is required due to the difference in pixel density between input and output devices.

Also, even with intelligent "P" etc. that have editing functions,
When an image is allocated to a specific area, pixel density conversion becomes center-to-center. However, in the 1411 images obtained by the systematic dither method described above, image quality deterioration due to moiré is reduced by 1 due to pixel density conversion. , 111 et al., the systematic dithering method compares the mxm pixel threshold matrix with the corresponding pixel values of the multivalued image and performs its binary representation. By binarization,...×m
The pattern of pixels is converted into a iii image in which the pattern is repeated. Even in a dithered image corresponding to a general multivalued image, periodicity as in the case of constant luminance described above naturally remains.

For this reason, a pixel density transformation of /11 is applied to the systematic digital image.
M and I irregularities occur in the converted image.

-h, Random dither images give periodicity to the image and are not distorted. Therefore, this random dither image is suitable for pixel density conversion, and in particular, a dither image based on the minimum mean error method, which is one of the random dither methods, is suitable for pixel density conversion, rather than a gradation image. Excellent in expression. The reason why the minimum average error method is not used despite this 'X @ 't11 property is that its hardware configuration is complex, as mentioned above.
This is because calculation time is required.

The present invention has been made in view of these circumstances, and uses a hidden coefficient of the minimum average error method, which can be expressed in the form of 2''N (where N is a natural number), to improve the hardware efficiency. We have realized a two-chain method and binarization device for both signals that can simplify the hardware configuration and shorten the processing time.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, before explaining the method of the present invention, let us first discuss the minimum average error method. The minimum average error method calculates the error of the binarized i-degree value of the determined window pixels around the pixel of interest with respect to the positive p-degree value, and calculates the error by a predetermined weighting coefficient to calculate the error of the 0-fold pixel. The corrected luminance value of the pixel of interest is calculated by adding it to the actual luminance value, and the modified 1F luminance value is compared with the threshold value. The direction is the sub-scanning direction), the pixels (X,
The actual brightness value of V) is Jx, y (0-R), the binarized brightness value of the pixel (x, y) is IX, V (O or R), the corrected brightness of the pixel (x, y) value J'
X pV N error EX, V=J'X+y Ix, y
Let the matrix of weighting coefficients (Ai,i> be
2) It can be found from Eq.

J'x+y=JX, V + input Aij・FX +, i
-3, V +-i -3 (2) 1 In addition, the binary numbers 1x and y are determined as follows according to the values of J'X and y.

lx, y = (Kun J'x...: R, / 2 curse;
J'xp...When R7/2 °°(3)
However, before C leading to pixel (3, 3), the needle stem of J'x+y is not formed, so the IF brightness value of this pixel is assumed to be, for example, J'xpy=JX,V, and the formula (3) is More l
Find x and y.

The above method is the minimum average error method C, but in this method, 'C' is expressed as △ii・Fx−+j− as shown in equation (2).
If we choose a matrix (Δii) of 6 weighting coefficients that requires a hanging frame of 3. In the example of Aij, 1/48.3/
48.5/48.7/48 is required, the hardware configuration is rough, and the frame speed is extremely low.

Therefore, in the method of the present invention, the above-mentioned hanging frame is
f) The elements of the matrix of coefficients (Aij) are reduced to 2-N so that the actual f-■"C can be obtained without using a tij
(However, N is a natural number) is selected to be a value that can be expressed in the form C (note that the sum of all elements is 1 or a fraction close to it). 7 tricks of this weighting coefficient (Aij> and C
I can give an example of the first order.

If selected in this way, it is possible to easily perform hanging by taking advantage of the characteristics of the digital part frame.

The binarization system of the present invention is an apparatus for concretely implementing the above-mentioned 21i111 (binarization method), and a block diagram of one embodiment is shown in FIG. The features of the binarization method and binarization device will be clarified.

In FIG. 2, J3 1 converts the image signal read by COD etc. into digital signal 4 △/D converter C1 In this embodiment, the digital signal (O to 127) is 8 It is output to the bit adder 1. The adder 1 is used to subtract 64 (RX2) from the output of the Δ/D converter 1 by 4 as preprocessing, to the complement of 64 = 11000000 (
(binary number) is given as the addend (see Figure 3).

3 and 7 are based on the weight coefficients in the first row of the latches 19 to 22 (second to sixth 8-bit adders C connected in one column, weight coefficient matrix <Ai, i). The error terms are respectively added to first adders 2. It is used to shore wire the outputs of the latches 19-22. 8 is a register connected to the adder 7, and the number of stages is n.
-5. However, n is the number of pixels (number of pixels) of one scanning line i'. 9-13 is lap 23~? The seventh to eleventh 8-bit adders ゛c are cascade-connected through 6, and the error terms based on the weighting coefficients in the second row of 7 tricks of weighting coefficients (Aij>) are transferred to the shift register 8. .Latch 23~
This is for adding 11iJ to the output of 26.

Reference numeral 14 denotes an 8-bit shift register connected to the adder 13, which has the same configuration as the shift register 8.

15 and 16 are connected via a latch 27, and shift the error term to the shift register 14. An 8-bit brightener 17 receives the output (J'x, y) of the adder 16 at the final stage through a latch 28 and a threshold value (in this embodiment, the adder 1 The threshold value is zero). The comparator 17 of this embodiment detects Ex and y rather than lx and y.

That is, when J'x+y≧0, lx,y=1 [×+ V -LJ 'x,y -64J'x +y
<0 throat tx, y =.

It outputs FX, V = J 'x, and y + 64, respectively, and its specific configuration is extremely simple (some examples exist), as shown in Figure 4.

When J'x+y≧0, [×, y are EX
, y =, ) 'x, y - (RX r
X, V64) --J'X
rV-(127X1-64)=J'x,y63, but MF, 3. As in IF < EX, V
= J'

(2) is required, so this configuration is more convenient.

In the comparator 17 having the configuration shown in FIG. 4, the positive and negative values of J'X #V are J,
(Focus on what is determined and make it into an inverter) ×
, y is +7. Also, in the calculation of Ex and y,
The complement of 64 is represented by the binary number 11000000, and 64
is the binary number oioo.

Since o o o 'r is expressed, the 1st bit (1-S
From bit 'B) to the 6th bit, the same value as J'x pv is used as the output of that bit of Ex, y, and only the upper two bits need to be calculated.

On top of this (one specific 172-bit operation is 1
There are 4 tables.

From this table, it can be seen that the upper two bits of [x, y take the same value and, moreover, take the opposite value to the 7th bit of J'x, y. Therefore, in the configuration shown in FIG. 4, J'x
The output of the 7th bit of pY is sent to E through an inverter.
The signals are the upper two bits of x and y.

-h output of comparator 17! × and ■ are sent to a recording device (not shown), while EX and V are input to the amplification section 18. In this embodiment C, a matrix of weighting coefficients (Δi, i)
For example, C1 uses (b) of the above examples. Therefore, in the calculation unit 18, 10-3.10', 10''5
EX, V to 11) Circuit part 18a for G
. , Furthermore, the output of the circuit section 18c is given to an adder 3.7.

In the present invention, the weighting coefficient △ij is in the form of 2 horizontal lines (2), so any failure in the circuit portions 18a to 18C can be achieved by simply shifting the bits to the first side.For this reason, the configuration is extremely simple. FIG. 5 shows the configuration of the circuit portion 18a, in which the bits lower than the 7th bit are shifted by 3 bits to the F-order bit side.

The circuit portions 18b and 18cL are constructed in the same manner. Therefore, a general hanging sieve is unnecessary.

In the inventive device configured as above, the input is 1)
The 1-1 image signal is digitally converted by a Δ/[) converter 1, subjected to a reduction process by an adder 2, and then sent to an adder 3. Initially, I0ro and I were set to "0",
C li for the first pixel (1°1)! Degree value J+, +
, nothing is added to the button and latch 19. Next, Jl,1 is latched in the latch 19 and input to the adder 4, and J2,1 is input to the adder 3.

Similarly, one after another, J+ and I are changed to Jino 1~,
The signal is supplied to the comparator 17 from the latch f28. Then, at C and A, 1 violet and 1 are found, and E + + + is also derived. Furthermore, El,1 is guided to the calculation section 18 and supplied to each exaggerator. At this time, as is clear from the number of adders 3 to 7 and 9 to 16 and the number of stages of shift registers 8 and 14, the image signals shown in the table below are input to each adder.

Therefore, in this circuit, 1, no, 1-, no, 1, J2, 1 = J? , ＋
10 Δ 3 * 2 F l +
1J3+I-J3+I +A3+2E2+1+
A! + t E + ・1 and the number of error additions gradually increases until Jl.

After 3, J'xzy=Jx, V +T, Aij-EX +J
3, V +1 3J will be output from the adder 16 (latch 28), and the comparator 17 will output 2
Output value signals 1x, y.

Also, in this circuit, the outputs of the brightening section 18 are ■ and ◎.

01 can be input by switching instead of inputting directly to each adder.
3 C is, for example, J'l, I, as taught by my predecessor.
The error terms due to ■, ◎, (3+ are J (TL −+
) , Q, Ja, (1(Q
= electricity,? ) I have a single husband so that I don't get married.

That is, when the human power of the comparator 17 is (a) J'+, V, the error term input of the adders 6.7 and 12.13 is (b) J2. When V, input the error term of adder 7.13, (C)J'n, when y, adder 3, 4.9.10.15-. When the error term input in 1.6 is (d) J'(,71-violet>,y, the eight error terms of adder 3.9.15 are set to rOJ, respectively. There is.

Of course, there are almost no problems in the peripheral area of the image, and 1
- Especially in the peripheral pixels as shown in (a) to (
It is also possible to execute h1 as is without inputting 101 to the adder listed in (1).

Incidentally, the shift 1 pulse of the register 8.14 and the timing pulses of the latches 19 to 28 are outputted from a control section (not shown) at timings to achieve the opening operation.

According to the book Y-book, it is possible to perform binarization based on the minimum average error method without using a general multiplier. The 8-bit addition sieve takes the longest calculation time! ? iiC
There is, but the main 1-ary lookahead method is 8L LJ.
If you use , for example, you can perform the performance in 36 ns. Therefore, tx, y is synchronized with the output of several MHz A/D converter.
A device that outputs this can also be easily configured.

As described above, according to the present invention, it is possible to realize an image signal binarization method and a binarization apparatus that can simplify the hardware configuration and shorten the performance time.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the arrangement of LJ pixels, Fig. 2 is a configuration diagram of a device (one embodiment of the device of the present invention) for realizing the present Komei method, and Fig. 3 is a diagram illustrating the arrangement of LJ pixels.
2 is a block diagram of the adder 2 in FIG. 2, FIG. 4 is a block diagram of the comparator 17 in FIG. 2, and FIG. 5 is a block diagram of the comparator 18 (
It is a block diagram of circuit part 18a). 1...Al1) Converter 2-7.9-13.15.16...Adder 8.14.
...Shift register 17...Comparator 18...Part frame part 18a,
18b, 1(llc--Circuit portions 19-28...
・Wrap patent applicant Roku Konishi Photo Industry Co., Ltd. Agent Patent attorney F Ijima Figure 1 Figure tail 3

Claims (2)

[Claims] (1) Calculate the error of the 2ts converted luminance value in the predetermined pixels around the pixel of interest with respect to the corrected luminance value, multiply the error by a predetermined weighting coefficient11, and calculate this as the actual luminance PXm of the pixel of interest.
In the image signal directization method, in which a corrected brightness value of the pixel of interest is obtained by adding weight to the pixel of interest, and a binarized signal is obtained by comparing the corrected brightness value with a threshold value, the weighting factor is 2min (however, A method for binarizing an image signal, characterized in that it uses a signal that can be expressed in the form (N is a natural number). (2) An A/D converter that digitally converts an input image signal, and a plurality of adders and shifters connected in cascade in an arrangement corresponding to the matrix of weighting coefficients on the output stage side of the A/D converter. The corrected luminance value outputted from the last adder among the plurality of adders between songs is compared with the threshold value, and the comparator outputs 1g, and the binarized signal A weighting factor is applied to the error applied to the corrected luminance value of l)
and an operator for supplying the obtained signal to the adder, and the weighting coefficient is selected to be a value that can be expressed in the form of 2min (where N is a natural number). A binarization device for image signals that correspond to features.