JPH0354511B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image signal binarization device using the minimum average error method, and more specifically, the present invention relates to an image signal binarization device that uses the minimum average error method, and more specifically, it calculates the error of the binarized luminance value of the predetermined pixels around the pixel of interest relative to the corrected luminance value, and sets the error to a predetermined value. A modified luminance value of the pixel of interest is obtained by multiplying by a weighting coefficient of , and this is added to the actual luminance value of the pixel of interest, and a binarized signal is obtained by comparing the modified luminance value with a threshold value. The present invention relates to a signal binarization method and a binarization device. According to the dither method, halftones can be substantially expressed at two levels, black and white, so this method has recently attracted attention and is beginning to be adopted in facsimiles and the like. There are two types of dithering methods: systematic dithering and random dithering, but due to the simplicity of the hardware configuration,
The former systematic dither method is used, and the latter random dither method is rarely used. Incidentally, in an image transmission system, pixel density conversion is required due to differences in pixel density between input and output devices. Furthermore, even with intelligent copying that has an editing function, pixel density conversion is required when allocating an image to a specific area. However, in the dithered image obtained by the systematic dithering method described above, image quality deterioration due to moiré occurs due to pixel density conversion. That is, in the systematic dither method, a threshold value matrix of m×m pixels is compared with the value of the corresponding pixel of a multivalued image, and its binary representation is performed. By valorization,
The image is converted into an image in which a pattern of m×m pixels is repeatedly arranged. Even in a dithered image for a general multivalued image, periodicity as in the case of constant brightness described above naturally remains. Therefore, when a systematic dither image is subjected to pixel density conversion, moiré occurs in the converted image. On the other hand, in a random dither image, periodicity is not given to the image. Therefore, this random dither image is suitable for pixel density conversion, and in particular, a dither image based on the minimum mean error method, which is one of the random dither methods, is not only suitable for pixel density conversion, but also It is also excellent in tonal expression. Despite these advantages, the reason why the minimum average error method is not used is that its hardware configuration is complicated, as described above. The present invention was made in view of the above circumstances, and it is possible to improve the hardware configuration by using a weighting coefficient that can be expressed in the form of 2 ^-N (where N is a natural number) as a weighting coefficient for the minimum average error method. The present invention realizes an image signal binarization device that can be simplified and the calculation time can be shortened. Hereinafter, the present invention will be explained in detail with reference to the drawings. First, prior to explaining the method of the present invention, the minimum average error method will be described. The minimum average error method calculates the error of the binarized brightness values of predetermined pixels around the pixel of interest with respect to the corrected brightness value, multiplies the error by a predetermined weighting coefficient, and adds it to the actual brightness value of the pixel of interest. This method calculates the corrected brightness value of the pixel of interest and compares the corrected brightness value with a threshold value. Specifically, as shown in Figure 1 (the x direction is the main scanning direction and the y direction is the sub scanning direction), , the actual brightness value of the pixel (x, y) of the multivalued image is Jx, y (O~R), and the corresponding pixel (x, y) is
y) is the binarized luminance value Ix, y (O or R), the corrected luminance value of the pixel (x, y) is J′ _x , _y , and the error is
Ex, _y = J'
/48 1/48 3/48 5/48 7/48 5/48 3/48 5/48 7/48* ...(1) However, if *; is the pixel of interest, then the corrected luminance value J' _x,y is obtained from the following equation (2). J′ _x,y = Jx, y+ 〓 ^ij Aij・Ex +j−3, y+i−3 …(2) Then, the binary signals Ix, y are changed as follows according to the values of J′ _x,y. can be determined. Ix, y = R; O when J' _{x ,y} ≧R/2; when J' Since _{x, y} cannot be calculated, the corrected brightness value up to this pixel is, for example, J′ _{x, y} = Jx, y, and from equation (3),
Find Ix and y. The above method is the minimum average error method, but in this method, as shown in equation (2), Aij・Ex+j
-3, y+i-3 multiplication is required. If a weighting coefficient matrix (Aij) such as that shown in equation (1) is selected, a general multiplier must be used for this multiplication, and in the above Aij example, 1/48,
Multipliers are required to multiply by 3/48, 5/48, and 7/48, making the hardware configuration complex and the calculation speed extremely slow. Therefore, in the method of the present invention, the elements of the weighting coefficient matrix (Aij) are set to 2 ^-N (however,
(N is a natural number) (note that the sum of all elements is 1 or a value close to it). The following can be cited as an example of this weighting coefficient matrix (Aij). (a) 2 ^-4 2 ^-4 2 ^-4 2 ^-4 2 ^-4 〓2 ^-4 2 ^{-3 2 -3} 2 ^{-3 2 -4} 〓2
^-4 2 ^-3 * (b) 2 ^-5 2 ^{-4 2} -3 2 ^-4 2 ^-5 2 ^-4 2 ^{-3 2 -3} 2 -3 2 ^{-4 2 -4} 2 ^-3 * (c) 2 ^-5 2 ^-4 2 ^{-4 2 -4} 2 ^{-5 2 -4} 2 -3 2 ^-3 2 ^{-3 2 -4} 2 ^-3 2 ^-3 * (d) 2 ^-6 2 ^-4 2 ^-4 2 ^{- 5} 2 ^-6 2 ^-4 2 ^-3 2 ^-3 2 ^-3 2 ^-4 2 ^-4 2 ^-2 * (e) 2 ^-6 2 -5 ^{2 -4} 2 ^{-5 2 -6 2 -4} 2 ^-3 2 ^-3 2 ^-3 2 ^-5 2 ^-3 2 ^-2 * If you choose in this way, you can easily perform multiplication by taking advantage of the characteristics of digital operations. FIG. 2 shows a block diagram of an embodiment of the present invention. In FIG. 2, numeral 1 is an A/D converter that digitally converts an image signal read by a CCD, etc. In this embodiment, a 7-bit digital signal (0 to 127) is sent to an 8-bit adder 1. Output. Adder 1 is used to subtract 64 (R/2) from the output of A/D converter 1 as a preprocessing, and 64's complement A = 11000000 (binary number) is given as the addend ( (See Figure 3). 3-7 are latches 19-22
The second to sixth 8-bit adders connected in cascade via
This is for adding error terms based on the weighting coefficients of the rows to the outputs of the first adder 2 and latches 19 to 22, respectively. 8 is an 8-bit shift register connected to the adder 7, and the number of stages thereof is n-5. However, n is - the number of quantization (number of pixels) on the scanning line
It is. Reference numerals 9 to 13 denote seventh to eleventh 8-bit adders connected in series via latches 23 to 26, which respectively shift error terms based on the weighting coefficients in the second row of the weighting coefficient matrix (Aij). 8, for adding to the outputs of latches 23-26. Reference numeral 14 denotes an 8-bit shift register connected to the adder 13, which has the same configuration as the shift register 8. 15 and 16 are latch 2
7, and an 8-bit adder 17 for adding an error term to the outputs of the shift register 14 and latch 27, respectively, based on the weighting coefficient in the third row of the weighting coefficient matrix (Aij). This is a comparator which receives the output (J' _x,y ) of the adder 16 at the final stage via a latch 28 and compares it with a threshold value (in this embodiment, since the adder 1 is provided, the threshold value is zero). The comparator 17 of this embodiment has not only Ix and y but also Ex,
It also outputs y. That is, when J′ _x,y ≧0 Ix, y=1 Ex, y=J′ _x,y −64 When J′ _x,y <0 Ix, y=0 Ex, y=J′ _x,y +64 respectively, and its specific configuration is as follows.
As shown in FIG. 4, it is extremely simple. Ex, y when J' _x,y ≧0 is Ex, y=J' _{x, y} − (R 64) = J' _x,y -63 However, as mentioned above, even if we approximate Ex, y = J' _x,y -64, no particular problem arises.In fact, a simple configuration as shown in Fig. 4 Since Ex and y can be obtained from the comparator 17, this configuration is more convenient. In the comparator 17 having the configuration shown in FIG. 4, we pay attention to the fact that the sign of J' _{x ,y} is determined by the MSB of the output J'
I have obtained Ix and y. In addition, in the calculation of Ex, y, the complement of 64 is represented by the binary number 11000000, and 64 is represented by the binary number 01000000, so from the 1st bit (LSB) to the 6th bit, J' _x,y It is only necessary to use the same value as the output of that bit of Ex and y and calculate only the upper two bits. The table below shows a concrete calculation of the upper two bits.

[Table] From this table, it can be seen that the 2nd bit of Ex and y take the same value and, moreover, take the opposite value to the 7th bit of J'x _,y . Therefore, in the configuration shown in Figure 4,
The output of the 7th bit of J'x _,y is passed through an inverter as a signal of the upper two bits of Ex,y. One output Ix, y of the comparator 17 is sent to a recording device (not shown), etc., while Ex, y are input to the calculation unit 18. In this embodiment, the weighting coefficient matrix (Aij) shown in (b) of the above examples is used. Therefore, in the arithmetic unit 18, 10 ^-3 ,
Circuit part 1 for multiplying Ex and y by 10 ^-4 and 10 ^-5
8a, 18b, and 18c, the output of the circuit section 18a is given to the adders 5, 10 to 12, and 16, and the output of the circuit section 18b is given to the adders 4, 6, and
9, 13, 15, and the circuit section 18c
The outputs of are given to adders 3 and 7. In the present invention, since the weighting factor Aij is of the form 2 ^-N , the multiplication in the circuit portions 18a-18c only requires bit shifting. For this reason,
Its configuration is extremely simple. Fifth
The figure shows the configuration of the circuit portion 18a, in which the bits lower than the seventh bit are shifted by three bits to the lower bit side. Circuit part 1
8b and 18c are similarly configured. Therefore, a general multiplier is not necessary. In the inventive device having the above configuration, an input analog image signal is digitally converted by the A/D converter 1, subjected to subtraction processing by the adder 2, and inputted to the adder 3. Initially, A, B, and C are set to "0", and the luminance value _J1,1 for the first pixel (1,1) is input to the latch 19 without being added to anything. Next, J _1,1 is latched in latch 19 and input to adder 4, and J _2,1 is input to adder 3.
is input. Similarly, J _1,1 is shifted one after another and is supplied to the comparator 17 by the latch 28. Then, I _1,1 is determined, and E _1,1 is also calculated. Furthermore, E _1,1 is guided to the calculation unit 18,
Supplied to each adder. At this time, adders 3 to 7,
As is clear from the numbers 9 to 16 and the number of stages of shift registers 8 and 14, the image signals shown in the table below are input to each adder.

[Table] Therefore, in this circuit, J' _1,1 = J _1,1 J' _2,1 = J _2,1 + A _3,2 E _1,1 J' _3,1 = J _3,1 + A _{3 ,2} E _2,1 +A _3,1 E _1,1 , the number of error additions gradually increases, and after J _3,3 , J′ _x,y = Jx, y+ 〓 ^ij Aij・Ex +j− 3, y+i-3 is output from the adder 16 (latch 28), and the comparator 17 outputs binary signals Ix, y corresponding to the positive/negative of this J' _x,y . In addition, in this circuit, the outputs of the arithmetic unit 18 ○a, ○b,
○ Since "0" can be inputted by switching instead of directly inputting C to each adder, for pixels in the peripheral area, for example, as can be seen from the table above, J' _1,1 The error terms ○a, ○ro, ○ha due to J( _o-
1 ),
We are trying not to add it to l, Jn, l (l = _1,2 ). That is, when the input of the comparator 17 is (a) J' ₁ , y, the error term input of adders 6, 7, 12, 13, (b) when J' ₂ , y, the adder (c) When J'n, y, the error term inputs of adders 3, 4, 9, 10, 15, 16, (d) J' ( _o-1 ) , y, the error term inputs of adders 3, 9, and 15 are each set to "0". Of course, there is almost no problem in the peripheral area of the image, but as mentioned above, the above problem is especially true in the peripheral pixels.
It is also possible to execute calculations as they are without inputting "0" to the adders listed in (a) to (d). Incidentally, shift pulses for the shift registers 8 and 14, timing pulses for the latches 19 to 28, etc. are outputted from a control section (not shown) at timings that achieve the above operations. According to the above-described apparatus of the present invention, binarization can be performed based on the minimum average error method, generally without using a multiplier. The 8-bit adder takes the longest calculation time in this device, but if a carry-look-ahead type ALU or the like is used, the calculation can be performed in, for example, 36 ns. Therefore, it is possible to easily construct a device that outputs Ix and y in synchronization with the output of an A/D converter of several MHz. As described above, according to the present invention, it is possible to realize an image signal binarization device that can simplify the hardware configuration.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the pixel arrangement, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of the adder 2 in Fig. 2, and Fig. 4 is a block diagram of the adder 2 in Fig. 2. FIG. 5 is a block diagram of the comparator 17, and FIG. 5 is a block diagram of the arithmetic unit 18 (circuit portion 18a) in FIG. 1...A/D converter, 2-7, 9-13, 1
5, 16... Adder, 8, 14... Shift register, 17... Comparator, 18... Arithmetic unit, 18a,
18b, 18c...Circuit portion, 19-28...Latch.

Claims (1)

[Claims] 1. In determining the binarized luminance value of the pixel of interest,
Calculating the error of the binarized luminance value with respect to the luminance value before binarization for a determined pixel whose binarized luminance value has already been determined, which is a pixel around the pixel of interest that has a certain positional relationship with the pixel of interest, The error in each predetermined pixel is multiplied by a predetermined weighting coefficient determined by the positional relationship of each predetermined pixel with respect to the pixel of interest, and the value obtained thereby is added to the actual brightness value of the pixel of interest. 2 of the image signal using the minimum average error method, which calculates a corrected brightness value and obtains a binarized brightness value of the pixel of interest by comparing the corrected brightness value with a threshold value.
The digitizing device includes an A/D converter that digitally converts an input image signal, and an A/D converter connected to the output stage side of the A/D converter and connected in cascade in an array corresponding to each element of the weighting coefficient matrix. corrected brightness value calculation means comprising an adder and a shift register, and outputs a corrected brightness value of a pixel of interest from the last adder of the plurality of adders; and the last stage of the plurality of adders. a comparator that compares the corrected brightness value output from the adder with a threshold value and outputs a binarized brightness value of the pixel of interest; and an error of the binarized brightness value outputted by the comparator with respect to the corrected brightness value. is multiplied by each weighting coefficient, and each obtained signal is input as an addition input to an adder in the corrected brightness value calculation means located at a position corresponding to the element position of each weighting coefficient in the matrix of weighting coefficients. a calculation unit for supplying the data, and a circuit portion in the calculation unit that multiplies the error of the binarized luminance value with respect to the corrected luminance value by each weighting coefficient has a configuration in which the weighting coefficient is 2 ^−N (however, N is selected as a value that can be expressed in the form of a natural number), and
An apparatus for binarizing an image signal, characterized in that the multiplication is performed by shifting the digital value of the error by N bits to the lower bit side.