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JPS5668833A - Shift process system by multiplier - Google Patents

Shift process system by multiplier

Info

Publication number
JPS5668833A
JPS5668833A JP14525579A JP14525579A JPS5668833A JP S5668833 A JPS5668833 A JP S5668833A JP 14525579 A JP14525579 A JP 14525579A JP 14525579 A JP14525579 A JP 14525579A JP S5668833 A JPS5668833 A JP S5668833A
Authority
JP
Japan
Prior art keywords
register
shift
multiplier
result
shift process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14525579A
Other languages
Japanese (ja)
Inventor
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14525579A priority Critical patent/JPS5668833A/en
Publication of JPS5668833A publication Critical patent/JPS5668833A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the quantity of the hardware exclusive for shift, by carrying out a shift process by use of the multiplier capable of the pipeline operation.
CONSTITUTION: The number to be shifted of the register 5 is set directly to the register 1; while the shift number of the register 6 is converted through the decoding circuit 7 into the bit pattern corresponding to the shift number and the shift direction to be set to the register 2. Then a multiplication is given between the contents of the register 1 and that of the register 2 through the multiplier circuit 3, and the result of multiplication is delivered to the register 4. The result of the right shift is obtained at the bits of the higher half of the contents of the register 4, and the result of the left shift is obtained at the bits of the lower half respectively. Thus a shift process is performed by use of the circuit capable of the pipeline operation to reduce the quantity of the hardware exclusive for shift.
COPYRIGHT: (C)1981,JPO&Japio
JP14525579A 1979-11-09 1979-11-09 Shift process system by multiplier Pending JPS5668833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14525579A JPS5668833A (en) 1979-11-09 1979-11-09 Shift process system by multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14525579A JPS5668833A (en) 1979-11-09 1979-11-09 Shift process system by multiplier

Publications (1)

Publication Number Publication Date
JPS5668833A true JPS5668833A (en) 1981-06-09

Family

ID=15380897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14525579A Pending JPS5668833A (en) 1979-11-09 1979-11-09 Shift process system by multiplier

Country Status (1)

Country Link
JP (1) JPS5668833A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215169A (en) * 1982-06-08 1983-12-14 Konishiroku Photo Ind Co Ltd Method and device for binary coding picture signal
JPS6372222A (en) * 1986-09-13 1988-04-01 Pioneer Electronic Corp Multiplier circuit
EP0685787A1 (en) * 1994-05-26 1995-12-06 Motorola, Inc. Multibit shifting apparatus, data processor using same, and method therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS541016A (en) * 1977-06-04 1979-01-06 Akiyoshi Igeta Reverse operation speaker system
JPS54101634A (en) * 1978-01-27 1979-08-10 Panafacom Ltd Shift arithmetic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS541016A (en) * 1977-06-04 1979-01-06 Akiyoshi Igeta Reverse operation speaker system
JPS54101634A (en) * 1978-01-27 1979-08-10 Panafacom Ltd Shift arithmetic circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215169A (en) * 1982-06-08 1983-12-14 Konishiroku Photo Ind Co Ltd Method and device for binary coding picture signal
JPH0354511B2 (en) * 1982-06-08 1991-08-20
JPS6372222A (en) * 1986-09-13 1988-04-01 Pioneer Electronic Corp Multiplier circuit
EP0685787A1 (en) * 1994-05-26 1995-12-06 Motorola, Inc. Multibit shifting apparatus, data processor using same, and method therefor

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