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JPS5786180A - Memory device having address converting mechanism - Google Patents

Memory device having address converting mechanism

Info

Publication number
JPS5786180A
JPS5786180A JP55160758A JP16075880A JPS5786180A JP S5786180 A JPS5786180 A JP S5786180A JP 55160758 A JP55160758 A JP 55160758A JP 16075880 A JP16075880 A JP 16075880A JP S5786180 A JPS5786180 A JP S5786180A
Authority
JP
Japan
Prior art keywords
memory
converting mechanism
address
bit
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55160758A
Other languages
Japanese (ja)
Other versions
JPH0118457B2 (en
Inventor
Yasushi Fukunaga
Tadaaki Bando
Hidekazu Matsumoto
Yoshinari Hiraoka
Toshiyuki Ide
Takeshi Kato
Tetsuya Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP55160758A priority Critical patent/JPS5786180A/en
Priority to US06/320,934 priority patent/US4481573A/en
Priority to EP81109719A priority patent/EP0052370B1/en
Priority to CA000390161A priority patent/CA1173567A/en
Priority to DE8181109719T priority patent/DE3176512D1/en
Publication of JPS5786180A publication Critical patent/JPS5786180A/en
Publication of JPH0118457B2 publication Critical patent/JPH0118457B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To manage with only one virtual address converting mechanism in a system, by providing a memory control part with an address converting mechanism which converts an accessed virtual address into the actual address of a memory part. CONSTITUTION:Memory requests from a processor are all supplied as virtual addresses on a common bus 11 and set in a virtual address register 21; and a conversion table 30 is stored in a memory part 16, and a high-speed buffer (TLB) 22 wherein accessed address information is stored is provided at a control part. The V bit 61 and C bit 62 of the TLB22 indicate the current states of corresponding pages, and when the V bit 61 is a 0, it is shown that the contents of the corresponding page of the TLB22 are insignificant data; when a 1, 1, the paging of the page is in process and when a 1, 0, the page is stored in the memory part 16, showing memory access is possible. When the 1, 1, only access from a file control processor is permitted.
JP55160758A 1980-11-17 1980-11-17 Memory device having address converting mechanism Granted JPS5786180A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55160758A JPS5786180A (en) 1980-11-17 1980-11-17 Memory device having address converting mechanism
US06/320,934 US4481573A (en) 1980-11-17 1981-11-13 Shared virtual address translation unit for a multiprocessor system
EP81109719A EP0052370B1 (en) 1980-11-17 1981-11-16 A virtual storage data processing system
CA000390161A CA1173567A (en) 1980-11-17 1981-11-16 Shared virtual address translation unit for a multiprocessor system
DE8181109719T DE3176512D1 (en) 1980-11-17 1981-11-16 A virtual storage data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55160758A JPS5786180A (en) 1980-11-17 1980-11-17 Memory device having address converting mechanism

Publications (2)

Publication Number Publication Date
JPS5786180A true JPS5786180A (en) 1982-05-29
JPH0118457B2 JPH0118457B2 (en) 1989-04-05

Family

ID=15721823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55160758A Granted JPS5786180A (en) 1980-11-17 1980-11-17 Memory device having address converting mechanism

Country Status (1)

Country Link
JP (1) JPS5786180A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60221851A (en) * 1984-02-17 1985-11-06 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Data processor and memory access controller used therefor
JPH02289017A (en) * 1989-02-21 1990-11-29 Sun Microsyst Inc Method of data transfer in computer system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5072543A (en) * 1973-10-29 1975-06-16
JPS52130246A (en) * 1976-04-24 1977-11-01 Fujitsu Ltd Memory access control system
JPS5475964A (en) * 1977-11-30 1979-06-18 Toshiba Corp Data pre-fetch system
JPS55142476A (en) * 1979-04-24 1980-11-07 Nec Corp Address conversion system for information processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5072543A (en) * 1973-10-29 1975-06-16
JPS52130246A (en) * 1976-04-24 1977-11-01 Fujitsu Ltd Memory access control system
JPS5475964A (en) * 1977-11-30 1979-06-18 Toshiba Corp Data pre-fetch system
JPS55142476A (en) * 1979-04-24 1980-11-07 Nec Corp Address conversion system for information processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60221851A (en) * 1984-02-17 1985-11-06 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Data processor and memory access controller used therefor
JPH0531776B2 (en) * 1984-02-17 1993-05-13 Fuiritsupusu Furuuiranpenfuaburiken Nv
JPH02289017A (en) * 1989-02-21 1990-11-29 Sun Microsyst Inc Method of data transfer in computer system

Also Published As

Publication number Publication date
JPH0118457B2 (en) 1989-04-05

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