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JPS56157520A - Dma system without cycle steal - Google Patents

Dma system without cycle steal

Info

Publication number
JPS56157520A
JPS56157520A JP5982780A JP5982780A JPS56157520A JP S56157520 A JPS56157520 A JP S56157520A JP 5982780 A JP5982780 A JP 5982780A JP 5982780 A JP5982780 A JP 5982780A JP S56157520 A JPS56157520 A JP S56157520A
Authority
JP
Japan
Prior art keywords
memory
data
access
addresses
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5982780A
Other languages
Japanese (ja)
Inventor
Ryuichiro Oota
Minoru Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5982780A priority Critical patent/JPS56157520A/en
Publication of JPS56157520A publication Critical patent/JPS56157520A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To improve the processing efficiency, by causing the direct memory access device to access a private memory instead of the main memory device and by accessing the private memory to transfer data when data transfer is requested from an input/output device. CONSTITUTION:A private memory 9 can be accessed directly by the CPU and has extended addresses of addresses of addresses of the main memory device (not shown in figure) of the computer, and data can be read from and written to this private memory 9 independently of the main memory device. When data transfer is requested from an input/output device 6, a control device 8 for the direct memory access DMA accesses the memory 9 instead of the main memory device to transfer required data. As a result, the processing efficiency is improved in the CPU in respect to the access to the main storage device.
JP5982780A 1980-05-06 1980-05-06 Dma system without cycle steal Pending JPS56157520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5982780A JPS56157520A (en) 1980-05-06 1980-05-06 Dma system without cycle steal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5982780A JPS56157520A (en) 1980-05-06 1980-05-06 Dma system without cycle steal

Publications (1)

Publication Number Publication Date
JPS56157520A true JPS56157520A (en) 1981-12-04

Family

ID=13124443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5982780A Pending JPS56157520A (en) 1980-05-06 1980-05-06 Dma system without cycle steal

Country Status (1)

Country Link
JP (1) JPS56157520A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183667A (en) * 1984-03-02 1985-09-19 Nec Corp Information processing unit
JPS6134662A (en) * 1984-07-27 1986-02-18 Tokyo Juki Ind Co Ltd Microcomputer application equipment
JPS61183767A (en) * 1985-02-08 1986-08-16 Nec Corp Buffer memory controlling system
JPH0537312Y2 (en) * 1987-11-20 1993-09-21

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183667A (en) * 1984-03-02 1985-09-19 Nec Corp Information processing unit
JPH0157379B2 (en) * 1984-03-02 1989-12-05 Nippon Electric Co
JPS6134662A (en) * 1984-07-27 1986-02-18 Tokyo Juki Ind Co Ltd Microcomputer application equipment
JPS61183767A (en) * 1985-02-08 1986-08-16 Nec Corp Buffer memory controlling system
JPH0537312Y2 (en) * 1987-11-20 1993-09-21

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