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JPS57169984A - Address comparing system - Google Patents

Address comparing system

Info

Publication number
JPS57169984A
JPS57169984A JP56048622A JP4862281A JPS57169984A JP S57169984 A JPS57169984 A JP S57169984A JP 56048622 A JP56048622 A JP 56048622A JP 4862281 A JP4862281 A JP 4862281A JP S57169984 A JPS57169984 A JP S57169984A
Authority
JP
Japan
Prior art keywords
address
register
comparison
comparison circuit
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56048622A
Other languages
Japanese (ja)
Other versions
JPS6010336B2 (en
Inventor
Masahiro Kuriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56048622A priority Critical patent/JPS6010336B2/en
Publication of JPS57169984A publication Critical patent/JPS57169984A/en
Publication of JPS6010336B2 publication Critical patent/JPS6010336B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the size of a comparison circuit for an instruction execution execution stopping, by coinciding the address of a designated location through the use of information of the presence of a designated location as the address comparison object stored on a page table. CONSTITUTION:A TLB (Translation Lookaside Buffer) is accessed with an upper-order bit address of a logical address register 2, and a high level flag F of the designated location presence information as an address comparison object stored in a conversion real address RA and a page table is read and an FF6 is set. On the other hand, an in-page displacement DiSP set to a register 5 via the register 2 and the address from a comparison address register 9 are compared at a comparison circuit 8. A control output from an AND gate 10 is generated according to the high level output of the FF6 and a pair of high level outputs of the circuit 8. A stop controlling comparison circuit for imagined system execution instruction can be reduced with the constitution of only the in-page displacement components for the location address register and the address comparison circuit.
JP56048622A 1981-03-31 1981-03-31 Address comparison method Expired JPS6010336B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048622A JPS6010336B2 (en) 1981-03-31 1981-03-31 Address comparison method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048622A JPS6010336B2 (en) 1981-03-31 1981-03-31 Address comparison method

Publications (2)

Publication Number Publication Date
JPS57169984A true JPS57169984A (en) 1982-10-19
JPS6010336B2 JPS6010336B2 (en) 1985-03-16

Family

ID=12808498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048622A Expired JPS6010336B2 (en) 1981-03-31 1981-03-31 Address comparison method

Country Status (1)

Country Link
JP (1) JPS6010336B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61272841A (en) * 1985-05-28 1986-12-03 Sony Tektronix Corp Address detecting circuit
FR2611939A1 (en) * 1987-03-03 1988-09-09 Nec Corp Device for address translation including a buffer memory for address translation loaded with the presence bits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61272841A (en) * 1985-05-28 1986-12-03 Sony Tektronix Corp Address detecting circuit
FR2611939A1 (en) * 1987-03-03 1988-09-09 Nec Corp Device for address translation including a buffer memory for address translation loaded with the presence bits

Also Published As

Publication number Publication date
JPS6010336B2 (en) 1985-03-16

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