JPS5759251A - Variable-word-length data processing system of data flow computer - Google Patents
Variable-word-length data processing system of data flow computerInfo
- Publication number
- JPS5759251A JPS5759251A JP13283680A JP13283680A JPS5759251A JP S5759251 A JPS5759251 A JP S5759251A JP 13283680 A JP13283680 A JP 13283680A JP 13283680 A JP13283680 A JP 13283680A JP S5759251 A JPS5759251 A JP S5759251A
- Authority
- JP
- Japan
- Prior art keywords
- word
- address
- instruction
- data
- operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To improve the efficiency of data processing dealing with data differing in word length constituting with an instruction storage controller which controls data having optional word length, by providing a word-number counter and an address converting mechanism which uses the contents of the counter as part of a logical address. CONSTITUTION:Operand data is divided into each one-word token containing an instruction word address and information on an operand word, and they are transferred successively from an instruction processor 2 to an instruction storage controller 1. This controller 1 is provided with a storage part 10 for operand data, a counter 8 which counts word addresses of entires constituting the operand data, and a converting mechanism 9 which converts a logical address, consisting of linked contents of the counter 8 and the instruction word address, into the physical address of the operand storage part 10. Then an instruction control part 4 access the storage part 10 on the basis of the converted address from the converting mechanism 9 to read its contents.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13283680A JPS5759251A (en) | 1980-09-26 | 1980-09-26 | Variable-word-length data processing system of data flow computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13283680A JPS5759251A (en) | 1980-09-26 | 1980-09-26 | Variable-word-length data processing system of data flow computer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5759251A true JPS5759251A (en) | 1982-04-09 |
Family
ID=15090653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13283680A Pending JPS5759251A (en) | 1980-09-26 | 1980-09-26 | Variable-word-length data processing system of data flow computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5759251A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58186848A (en) * | 1982-04-23 | 1983-10-31 | Oki Electric Ind Co Ltd | Data flow processing method |
-
1980
- 1980-09-26 JP JP13283680A patent/JPS5759251A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58186848A (en) * | 1982-04-23 | 1983-10-31 | Oki Electric Ind Co Ltd | Data flow processing method |
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