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JPS5772331A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5772331A
JPS5772331A JP55148597A JP14859780A JPS5772331A JP S5772331 A JPS5772331 A JP S5772331A JP 55148597 A JP55148597 A JP 55148597A JP 14859780 A JP14859780 A JP 14859780A JP S5772331 A JPS5772331 A JP S5772331A
Authority
JP
Japan
Prior art keywords
silicon layer
layer
silicon
sloping surface
reactive ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55148597A
Other languages
Japanese (ja)
Inventor
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55148597A priority Critical patent/JPS5772331A/en
Publication of JPS5772331A publication Critical patent/JPS5772331A/en
Pending legal-status Critical Current

Links

Classifications

    • H10P14/6308—

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent polycrystalline silicon from remaining behind by making a peripheral edge part of a silicon dioxide layer a sloping surface in case where the polycrystalline silicon layer deposited on the silicon dioxide is removed selective by means of a reactive ion etching method. CONSTITUTION:An end part of a silicon dioxide layer 4 that becomes a mask is formed into a sloping surface. When reactive ion etching is executed for the silicon layer 4 and a polycrystalline silicon layer 2, said two layers 4, 2 are to have a continuous sloping surface. Then, such a structure is obtained that a side surface of the silicon layer 2 is oxidized and the surface of the silicon layer 2 is coated with the silicon layer 4. Hereby, it is permitted to prevent the silicon layer 2 from remaining.
JP55148597A 1980-10-23 1980-10-23 Manufacture of semiconductor device Pending JPS5772331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148597A JPS5772331A (en) 1980-10-23 1980-10-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148597A JPS5772331A (en) 1980-10-23 1980-10-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5772331A true JPS5772331A (en) 1982-05-06

Family

ID=15456309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148597A Pending JPS5772331A (en) 1980-10-23 1980-10-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5772331A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089436A (en) * 1987-09-21 1992-02-18 Samsung Semiconductor And Telecommunications Co., Ltd. Method for fabricating a semiconductor device by slope etching a polysiliow layer
US5100820A (en) * 1990-06-14 1992-03-31 Oki Electric Industry Co., Ltd. MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode
US5354716A (en) * 1990-05-02 1994-10-11 Nec Electronics, Inc. Method for forming a DRAM memory cell with tapered capacitor electrodes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089436A (en) * 1987-09-21 1992-02-18 Samsung Semiconductor And Telecommunications Co., Ltd. Method for fabricating a semiconductor device by slope etching a polysiliow layer
US5354716A (en) * 1990-05-02 1994-10-11 Nec Electronics, Inc. Method for forming a DRAM memory cell with tapered capacitor electrodes
US5100820A (en) * 1990-06-14 1992-03-31 Oki Electric Industry Co., Ltd. MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode

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