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JPS5750381A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5750381A
JPS5750381A JP55126705A JP12670580A JPS5750381A JP S5750381 A JPS5750381 A JP S5750381A JP 55126705 A JP55126705 A JP 55126705A JP 12670580 A JP12670580 A JP 12670580A JP S5750381 A JPS5750381 A JP S5750381A
Authority
JP
Japan
Prior art keywords
byte width
memory
buffer
data
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55126705A
Other languages
Japanese (ja)
Inventor
Koji Urata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55126705A priority Critical patent/JPS5750381A/en
Publication of JPS5750381A publication Critical patent/JPS5750381A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To produce a flank time which is not restricted by a memory reading buffer when a mishit arises and then to reduce the processing time of instruction, by writing the data into a cash memory with a byte width of integer times as much as the byte width that is read out of a main storage. CONSTITUTION:When a mishit arises, a memory reading buffer 5' reads the data out of a main storage 6 with N-byte width and writes it into a cash memory 4 with 2N-byte width. The data of N-byte width is stored temporarily in the buffer 5' until it obtains the 2N-byte width, and this storage time S is obtained between timings t6 and t7 plus t8 and t9 respectively. Meanwhile the memory 4 is not restricted by the buffer 5'. Accordingly the reading cycle R among the processing cycles of an instruction 2 which is parallel to the block loading cycle M can be processed simultaneously with and in parallel to the cycle M in the timing t8.
JP55126705A 1980-09-12 1980-09-12 Information processor Pending JPS5750381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55126705A JPS5750381A (en) 1980-09-12 1980-09-12 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55126705A JPS5750381A (en) 1980-09-12 1980-09-12 Information processor

Publications (1)

Publication Number Publication Date
JPS5750381A true JPS5750381A (en) 1982-03-24

Family

ID=14941807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55126705A Pending JPS5750381A (en) 1980-09-12 1980-09-12 Information processor

Country Status (1)

Country Link
JP (1) JPS5750381A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930289A (en) * 1982-08-06 1984-02-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Hierarchical memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930289A (en) * 1982-08-06 1984-02-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Hierarchical memory system
EP0100943A2 (en) * 1982-08-06 1984-02-22 International Business Machines Corporation Hierarchical memory system

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