JPS6450126A - System for hierarchizing cache memory - Google Patents

Abstract

PURPOSE:To suppress the increase of the hardware quantity, and also, to cope with a high speed conversion of a CPU, by providing a cache memory for storing an operand, and a cache memory for storing (n) pieces of continuous instructions. CONSTITUTION:In a first cache memory 11, an operand is stored, and in a second cache memory 12, (n) pieces (n is a positive integer of >=2) of continuous instructions can be stored. In this state, in case of prefetching a precedence instruction in parallel with the execution of an instruction by an instruction execution control part 20, the memory 12 is brought to an access by an instruction address held in a precedence instruction address register 15. Also, in case of being brought to an access through an operand address generating circuit 18, the memory 11 is brought to an access. That is, at the time of an operand access, the memory 11 whose capacity is not large is used, and at the time of an instruction access, continuous instructions are read out by using the memory 12 of a large capacity, and by executing successively its instructions, the increase of the hardware quantity is suppressed, and it is possible to cope with the high speed conversion of a CPU.