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JPS57208156A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57208156A
JPS57208156A JP9303681A JP9303681A JPS57208156A JP S57208156 A JPS57208156 A JP S57208156A JP 9303681 A JP9303681 A JP 9303681A JP 9303681 A JP9303681 A JP 9303681A JP S57208156 A JPS57208156 A JP S57208156A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
selectively
film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9303681A
Other languages
Japanese (ja)
Inventor
Yoshihide Nagakubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9303681A priority Critical patent/JPS57208156A/en
Publication of JPS57208156A publication Critical patent/JPS57208156A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the production of a defect due to the thermal influence at the time of selective oxidation by forming a material layer to be oxidized on a semiconductor substrate, selectively forming an antioxidative mask on the layer to selectively oxidize the layer and removing the mask and the remaining layer. CONSTITUTION:A P type single crystal silicon substrate 1 is thermally oxidized to grow a thermally oxidized film 2 on the main surface, a polycrystalline silicon is then grown in vapor phase, and a phosphorus-doped polycrystalline silicon layer 3 is accumulated. Then, a nitrided silicon pattern 4 is selectively formed as an antioxidative mask, a polycrystalline silicon layer 3 is selectively oxidized, thereby forming a thermally oxidized film 6. After the pattern 4 is then removed, the remaining polycrystalline silicon layer 3' is removed. Subsequently, the projections of plasma CVD SiO2 7 is formed covering the whole surface, and the SiO2 7 and the film 6 are substantially etched and removed. Then, an n-channel MOSIC is formed with the film 6 as an element isolating region.
JP9303681A 1981-06-18 1981-06-18 Manufacture of semiconductor device Pending JPS57208156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9303681A JPS57208156A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9303681A JPS57208156A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57208156A true JPS57208156A (en) 1982-12-21

Family

ID=14071262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9303681A Pending JPS57208156A (en) 1981-06-18 1981-06-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57208156A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263265A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of semiconductor device
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263265A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of semiconductor device
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

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