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JPS57207924A - Input and output interface device - Google Patents

Input and output interface device

Info

Publication number
JPS57207924A
JPS57207924A JP9299781A JP9299781A JPS57207924A JP S57207924 A JPS57207924 A JP S57207924A JP 9299781 A JP9299781 A JP 9299781A JP 9299781 A JP9299781 A JP 9299781A JP S57207924 A JPS57207924 A JP S57207924A
Authority
JP
Japan
Prior art keywords
input
data
bus
output
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9299781A
Other languages
Japanese (ja)
Other versions
JPS6028024B2 (en
Inventor
Tokutaro Shinpo
Kazuhiro Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP9299781A priority Critical patent/JPS6028024B2/en
Publication of JPS57207924A publication Critical patent/JPS57207924A/en
Publication of JPS6028024B2 publication Critical patent/JPS6028024B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reduce the number of connected lines, by connecting the input and the output of a bus which transmits data in time division system to each other and by installing a means which performs the address conversion of the input-output unit and the low-way transmission of data in accordance with the operational mode. CONSTITUTION:A data bus 31 transmits data and address dignals in time division system and an address converting circuit 33 connecets the CPU side (input) and the expanded side (output) of the bus 31 to tach other and performs two- way transmission of data by performing automaitc address conversions in accordance with operational mode signals sent from a CPU through a controller 32. Address signals of an input-outut unit sent from the bus 31 are displayed 39 after they are detected through a latch circuit 37 and a decorder 38, and address signals of cards are detected through a latch circuit 45 and a decoder 46 and an input-output card selecting signal CS is outputted. Data from the bus 31, input card transfer data DR and output card transfer data DW, are sent to selected cards through an input-output data bus 49 by a two-way bus driver 48.
JP9299781A 1981-06-18 1981-06-18 Input/output interface device Expired JPS6028024B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9299781A JPS6028024B2 (en) 1981-06-18 1981-06-18 Input/output interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9299781A JPS6028024B2 (en) 1981-06-18 1981-06-18 Input/output interface device

Publications (2)

Publication Number Publication Date
JPS57207924A true JPS57207924A (en) 1982-12-20
JPS6028024B2 JPS6028024B2 (en) 1985-07-02

Family

ID=14069997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9299781A Expired JPS6028024B2 (en) 1981-06-18 1981-06-18 Input/output interface device

Country Status (1)

Country Link
JP (1) JPS6028024B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188841A (en) * 1983-04-08 1984-10-26 Matsushita Electric Ind Co Ltd Optical information recording and reproducing device
WO1985003786A1 (en) * 1984-02-22 1985-08-29 Fanuc Ltd Method of selecting address in input/output board
JPS6230445U (en) * 1985-08-07 1987-02-24
US4755934A (en) * 1984-03-28 1988-07-05 Fanuc Ltd. System for selecting an address in an input/output board

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284842A (en) * 1991-03-13 1992-10-09 Seven Ribaa:Kk Super-solubilized dispersion stirring and supply tank

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188841A (en) * 1983-04-08 1984-10-26 Matsushita Electric Ind Co Ltd Optical information recording and reproducing device
JPH0533462B2 (en) * 1983-04-08 1993-05-19 Matsushita Electric Ind Co Ltd
WO1985003786A1 (en) * 1984-02-22 1985-08-29 Fanuc Ltd Method of selecting address in input/output board
US4755934A (en) * 1984-03-28 1988-07-05 Fanuc Ltd. System for selecting an address in an input/output board
JPS6230445U (en) * 1985-08-07 1987-02-24

Also Published As

Publication number Publication date
JPS6028024B2 (en) 1985-07-02

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