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JPS5776621A - Data processing system having input and output system - Google Patents

Data processing system having input and output system

Info

Publication number
JPS5776621A
JPS5776621A JP55152838A JP15283880A JPS5776621A JP S5776621 A JPS5776621 A JP S5776621A JP 55152838 A JP55152838 A JP 55152838A JP 15283880 A JP15283880 A JP 15283880A JP S5776621 A JPS5776621 A JP S5776621A
Authority
JP
Japan
Prior art keywords
data
sink
signal
bus
crc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55152838A
Other languages
Japanese (ja)
Inventor
Hisashi Kimura
Kiyoo Moroto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55152838A priority Critical patent/JPS5776621A/en
Publication of JPS5776621A publication Critical patent/JPS5776621A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To eliminate the limitation of bus length, by setting up a bus before receiving a sink-signal from a reception side and then sending data successively from a transmission side. CONSTITUTION:When an input-output controller 2 sends data 1, data 2...successively, the controller 2 permits a CRC(cyclic redundancy check) generation part 11 to generate CRC characters corresponding to the data, and adds the corresponding CRC characters to parts close to the ends of the data, thereby sending them onto a bus-in line 3 through the driving circuit 7. At this time, a sink-in signal is sent out corresponding to the data 1. Then, a bus is set up without waiting for the arrival of a sink-out signal, and the controller 2 sends the data 2 together with a corressponding sink-in signal. Similarly, the data 3, data 4... are sent out and the said CRC characters are added corresponding to the data.
JP55152838A 1980-10-30 1980-10-30 Data processing system having input and output system Pending JPS5776621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55152838A JPS5776621A (en) 1980-10-30 1980-10-30 Data processing system having input and output system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55152838A JPS5776621A (en) 1980-10-30 1980-10-30 Data processing system having input and output system

Publications (1)

Publication Number Publication Date
JPS5776621A true JPS5776621A (en) 1982-05-13

Family

ID=15549231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55152838A Pending JPS5776621A (en) 1980-10-30 1980-10-30 Data processing system having input and output system

Country Status (1)

Country Link
JP (1) JPS5776621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146541A (en) * 1984-08-11 1986-03-06 Fujitsu Ltd Data writing method
WO1996041424A1 (en) * 1995-06-07 1996-12-19 Micron Technology, Inc. High speed cyclical redundancy check system using a programmable architecture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146541A (en) * 1984-08-11 1986-03-06 Fujitsu Ltd Data writing method
WO1996041424A1 (en) * 1995-06-07 1996-12-19 Micron Technology, Inc. High speed cyclical redundancy check system using a programmable architecture
US5854800A (en) * 1995-06-07 1998-12-29 Micron Technlogy, Inc. Method and apparatus for a high speed cyclical redundancy check system
US5964896A (en) * 1995-06-07 1999-10-12 Micron Technology, Inc. Method and apparatus for a high speed cyclical redundancy check system

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