JPS5727330A - Process control device - Google Patents
Process control deviceInfo
- Publication number
- JPS5727330A JPS5727330A JP10127680A JP10127680A JPS5727330A JP S5727330 A JPS5727330 A JP S5727330A JP 10127680 A JP10127680 A JP 10127680A JP 10127680 A JP10127680 A JP 10127680A JP S5727330 A JPS5727330 A JP S5727330A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- output
- computer
- input
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Control By Computers (AREA)
Abstract
PURPOSE:To perform controlling inexpensively with high reliability with a simple procedure by transmitting and receiving information between a computer bus and a process input and output bus by way of bus decoders and transmission lines, and stopping the operation of the computer during that time. CONSTITUTION:To make output operation, the address and output data of a digital output device 9 are placed onto a computer bus BC from a computer 1, and an input/output signal is made into output mode. The address and data are placed on a process input and output bus BP by a bus decoder 2 via a parallel to series converter 4 and a series to parallel converter 6, and the device 9 outputs required data. To make input operation next, the signal is fed to a stopping device 3 by the decoder 2 to stop the operation of the computer 1, and the address value is converted 4, 6, and is transmitted onto the bus BP. The input data is transmitted to the bus BC by a bus decoder 8 via a parallel to series converter 7 and a series to parallel converter 5; at the same time a release signal is fed from the device 5 to the device 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10127680A JPS5727330A (en) | 1980-07-25 | 1980-07-25 | Process control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10127680A JPS5727330A (en) | 1980-07-25 | 1980-07-25 | Process control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5727330A true JPS5727330A (en) | 1982-02-13 |
Family
ID=14296348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10127680A Pending JPS5727330A (en) | 1980-07-25 | 1980-07-25 | Process control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5727330A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278654A (en) * | 1985-10-02 | 1987-04-10 | Alps Electric Co Ltd | Remote terminal control system |
| WO2005048115A2 (en) * | 2003-11-13 | 2005-05-26 | Koninklijke Philips Electronics N.V. | Electronic data processing circuit that transmits packed words via a bus |
-
1980
- 1980-07-25 JP JP10127680A patent/JPS5727330A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278654A (en) * | 1985-10-02 | 1987-04-10 | Alps Electric Co Ltd | Remote terminal control system |
| WO2005048115A2 (en) * | 2003-11-13 | 2005-05-26 | Koninklijke Philips Electronics N.V. | Electronic data processing circuit that transmits packed words via a bus |
| WO2005048115A3 (en) * | 2003-11-13 | 2005-07-14 | Koninkl Philips Electronics Nv | Electronic data processing circuit that transmits packed words via a bus |
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