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JPS57166759A - Controlling method for common input/output bus - Google Patents

Controlling method for common input/output bus

Info

Publication number
JPS57166759A
JPS57166759A JP56051117A JP5111781A JPS57166759A JP S57166759 A JPS57166759 A JP S57166759A JP 56051117 A JP56051117 A JP 56051117A JP 5111781 A JP5111781 A JP 5111781A JP S57166759 A JPS57166759 A JP S57166759A
Authority
JP
Japan
Prior art keywords
frame
station
computer
comparator
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56051117A
Other languages
Japanese (ja)
Other versions
JPH0223060B2 (en
Inventor
Hiroshi Kobayashi
Hiroaki Nakanishi
Hideo Yanai
Yasushi Fukunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56051117A priority Critical patent/JPS57166759A/en
Publication of JPS57166759A publication Critical patent/JPS57166759A/en
Publication of JPH0223060B2 publication Critical patent/JPH0223060B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make a station use a computer exclusively in a system in which plural computers and plural stations are connected to a loop bus. CONSTITUTION:A frame transmitted by a loop bus 7 is sent to the loop bus 7 again through a receiving buffer 31 and a transmitting buffer 30. A station 8 determines whether the frame is to be entered in the station or not by a register 16A and a comparator 17A in case of the frame for a specific station or a register 16B and a comparator 17B in case of the frame for common stations. When the station 8 is used by a specific computer exclusively, a frame indicating exclusive use is sent to the station 8, which sets up the station address of the said computer on a register 16C by the frame and sets up a switching circuit 22 so as to output ''0''. Thus, if frame is not outputted from the said computer, a comparator 17C is not turned to ''1'', an AND circuit 21 does not operate and the frame is not entered.
JP56051117A 1981-04-07 1981-04-07 Controlling method for common input/output bus Granted JPS57166759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051117A JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051117A JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Publications (2)

Publication Number Publication Date
JPS57166759A true JPS57166759A (en) 1982-10-14
JPH0223060B2 JPH0223060B2 (en) 1990-05-22

Family

ID=12877858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051117A Granted JPS57166759A (en) 1981-04-07 1981-04-07 Controlling method for common input/output bus

Country Status (1)

Country Link
JP (1) JPS57166759A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130647A (en) * 1982-01-29 1983-08-04 Nec Corp Loop type data transmitting system
JPS5986353A (en) * 1982-11-09 1984-05-18 Toshiba Corp Data transmitter
JPS59228444A (en) * 1983-06-10 1984-12-21 Canon Inc Communication system
JPS61145670A (en) * 1984-12-19 1986-07-03 Nec Corp Multi-processor system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336120A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Information transfer system
JPS54163607A (en) * 1978-06-15 1979-12-26 Nissin Electric Co Ltd Data sorting system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336120A (en) * 1976-09-16 1978-04-04 Fujitsu Ltd Information transfer system
JPS54163607A (en) * 1978-06-15 1979-12-26 Nissin Electric Co Ltd Data sorting system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130647A (en) * 1982-01-29 1983-08-04 Nec Corp Loop type data transmitting system
JPS5986353A (en) * 1982-11-09 1984-05-18 Toshiba Corp Data transmitter
JPS59228444A (en) * 1983-06-10 1984-12-21 Canon Inc Communication system
JPS61145670A (en) * 1984-12-19 1986-07-03 Nec Corp Multi-processor system

Also Published As

Publication number Publication date
JPH0223060B2 (en) 1990-05-22

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