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JPS57158080A - Semiconductor memory device using serial data transfer system - Google Patents

Semiconductor memory device using serial data transfer system

Info

Publication number
JPS57158080A
JPS57158080A JP56044280A JP4428081A JPS57158080A JP S57158080 A JPS57158080 A JP S57158080A JP 56044280 A JP56044280 A JP 56044280A JP 4428081 A JP4428081 A JP 4428081A JP S57158080 A JPS57158080 A JP S57158080A
Authority
JP
Japan
Prior art keywords
cycle
data
counter
signal
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56044280A
Other languages
Japanese (ja)
Inventor
Hisateru Horie
Kenzo Ito
Yoshio Hirano
Kazufumi Akutsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP56044280A priority Critical patent/JPS57158080A/en
Publication of JPS57158080A publication Critical patent/JPS57158080A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/04Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To store and reproduce a large volume of data at a high speed by storing and reproducing data non-synchronously without requiring a synchronous signal and readout/writing one bit in one cycle of a clock signal. CONSTITUTION:In a chip selection cycle, a counter 3 is reset initially by the leading edge 30 of a reset signal and activated under the high level. After the end of the cycle, the reset signal goes down to the low level and the cycle is turned to an address-up memory reading/writing cycle; during the cycle, outputs from the counter 3 are continued to be latched. A counter 4 counts up in every decay of a clock signal and specifies memory locations successively and a data with the specified address is outputted to a data output signal to read out data.
JP56044280A 1981-03-26 1981-03-26 Semiconductor memory device using serial data transfer system Pending JPS57158080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56044280A JPS57158080A (en) 1981-03-26 1981-03-26 Semiconductor memory device using serial data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56044280A JPS57158080A (en) 1981-03-26 1981-03-26 Semiconductor memory device using serial data transfer system

Publications (1)

Publication Number Publication Date
JPS57158080A true JPS57158080A (en) 1982-09-29

Family

ID=12687091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56044280A Pending JPS57158080A (en) 1981-03-26 1981-03-26 Semiconductor memory device using serial data transfer system

Country Status (1)

Country Link
JP (1) JPS57158080A (en)

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