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JPS56153597A - Mass storage device - Google Patents

Mass storage device

Info

Publication number
JPS56153597A
JPS56153597A JP5738980A JP5738980A JPS56153597A JP S56153597 A JPS56153597 A JP S56153597A JP 5738980 A JP5738980 A JP 5738980A JP 5738980 A JP5738980 A JP 5738980A JP S56153597 A JPS56153597 A JP S56153597A
Authority
JP
Japan
Prior art keywords
data
designated
readout
signal
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5738980A
Other languages
Japanese (ja)
Inventor
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5738980A priority Critical patent/JPS56153597A/en
Publication of JPS56153597A publication Critical patent/JPS56153597A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To quickly enable the test every mounting unit, by comparing the data written in the storage means selected and designated with the readout data for agreement. CONSTITUTION:At write-in operation, the memory module is designated with the memory module selection signal 13, readout/write-in control signal 14 is designated in write-in state and the write-in data 11 is written in the address designated from the address signal. In case of readout operation, the signal 14 is designated into readout state while the signal 13 is in selecting state. When one-bit in arbitrary n- word in the memory module 1 is designated with the signal 15, it is read out as the readout data 12. The data 12 and the expectation value being the data 11 are compared every corresponding bit in the comparison circuit 2 and the coincidence is output as the comparison result signal 16. As a result, if the data written in advance is correctly readout or not can be discriminated every memory module.
JP5738980A 1980-04-30 1980-04-30 Mass storage device Pending JPS56153597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5738980A JPS56153597A (en) 1980-04-30 1980-04-30 Mass storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5738980A JPS56153597A (en) 1980-04-30 1980-04-30 Mass storage device

Publications (1)

Publication Number Publication Date
JPS56153597A true JPS56153597A (en) 1981-11-27

Family

ID=13054253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5738980A Pending JPS56153597A (en) 1980-04-30 1980-04-30 Mass storage device

Country Status (1)

Country Link
JP (1) JPS56153597A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989010593A1 (en) * 1988-04-28 1989-11-02 Fanuc Ltd Memory testing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989010593A1 (en) * 1988-04-28 1989-11-02 Fanuc Ltd Memory testing system

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