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JPS56159885A - Storage device - Google Patents

Storage device

Info

Publication number
JPS56159885A
JPS56159885A JP6254680A JP6254680A JPS56159885A JP S56159885 A JPS56159885 A JP S56159885A JP 6254680 A JP6254680 A JP 6254680A JP 6254680 A JP6254680 A JP 6254680A JP S56159885 A JPS56159885 A JP S56159885A
Authority
JP
Japan
Prior art keywords
data
line
address
read
row address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6254680A
Other languages
Japanese (ja)
Other versions
JPS6321276B2 (en
Inventor
Koichiro Omoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6254680A priority Critical patent/JPS56159885A/en
Publication of JPS56159885A publication Critical patent/JPS56159885A/en
Publication of JPS6321276B2 publication Critical patent/JPS6321276B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To elevate the processing capacity of a storage device, by accessing the memory array at the same time and executing the parallel processing of request, when the address to be referred to are continued and a great deal of data are read and written. CONSTITUTION:A line of the memory array is accessed through the line address decoder, and a data of one line is read out. Each data is inputted to the selecting circuit group 99 through the sense amplifier 16-2 corresponding to the bit. These circuit groups 99 are controlled in accordance with the decoding result of the row address from the row address buffer by the row decoder groups 18-1..., and only a data corresponding to a specific bit which has been designated by the row address is outputted through the corresponding circuit group 99. On the other hand, a read- out data of one line portion from the amplifier group 16-2 is provided to the data output buffer 37 without passing through the circuit group 99. Write can be executed in the same way, and the parallel processing of request becomes possible.
JP6254680A 1980-05-12 1980-05-12 Storage device Granted JPS56159885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6254680A JPS56159885A (en) 1980-05-12 1980-05-12 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6254680A JPS56159885A (en) 1980-05-12 1980-05-12 Storage device

Publications (2)

Publication Number Publication Date
JPS56159885A true JPS56159885A (en) 1981-12-09
JPS6321276B2 JPS6321276B2 (en) 1988-05-06

Family

ID=13203336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6254680A Granted JPS56159885A (en) 1980-05-12 1980-05-12 Storage device

Country Status (1)

Country Link
JP (1) JPS56159885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182586A (en) * 1984-02-29 1985-09-18 Nec Corp Memory integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019214140B4 (en) 2019-09-17 2023-11-02 Adidas Ag Glove, especially goalkeeper glove

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182586A (en) * 1984-02-29 1985-09-18 Nec Corp Memory integrated circuit

Also Published As

Publication number Publication date
JPS6321276B2 (en) 1988-05-06

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