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JPS57153468A - Insulated gate type field effect transistor - Google Patents

Insulated gate type field effect transistor

Info

Publication number
JPS57153468A
JPS57153468A JP56037805A JP3780581A JPS57153468A JP S57153468 A JPS57153468 A JP S57153468A JP 56037805 A JP56037805 A JP 56037805A JP 3780581 A JP3780581 A JP 3780581A JP S57153468 A JPS57153468 A JP S57153468A
Authority
JP
Japan
Prior art keywords
gates
minuteness
constitution
substrate
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56037805A
Other languages
Japanese (ja)
Inventor
Tamotsu Ohata
Hirohito Tanabe
Yukinobu Miwa
Takeshi Kuramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56037805A priority Critical patent/JPS57153468A/en
Publication of JPS57153468A publication Critical patent/JPS57153468A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Abstract

PURPOSE:To improve minuteness and yeidl rate by a method wherein a plurality of heat resisting gates are formed through insulation film on an Si substrate, a channel base and source are provided by a self-matching and the gates are connected with metallic wire. CONSTITUTION:N type Si substrate 1 is used for a drain, gates 12, 12<1> ... obtained by dividing polysilicon or Mo silicide, etc. are formed through gate oxide film 11 on a main face, channel base 13 and source 14 are provided by a double diffusion of P, N type impurities by use for a mask of the gates, while the gates are covered with oxide thick film 15, an opening is provided selectively, Al is mounted over the entire surface to be connected, and electrodes 16G, 16S are formed on the surface and electrode 16D is formed on the back surface. According to such a constitution, when forming a gate oxide film, a photo- etching becomes unnecessary, the minuteness can be achieved, the yeild rate also be improved, the circumferential length be extended because of the divided gates, while a parasitic capacity be reduced and further the distribution of the impurity be controlled easily.
JP56037805A 1981-03-18 1981-03-18 Insulated gate type field effect transistor Pending JPS57153468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56037805A JPS57153468A (en) 1981-03-18 1981-03-18 Insulated gate type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56037805A JPS57153468A (en) 1981-03-18 1981-03-18 Insulated gate type field effect transistor

Publications (1)

Publication Number Publication Date
JPS57153468A true JPS57153468A (en) 1982-09-22

Family

ID=12507722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56037805A Pending JPS57153468A (en) 1981-03-18 1981-03-18 Insulated gate type field effect transistor

Country Status (1)

Country Link
JP (1) JPS57153468A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01238174A (en) * 1988-03-18 1989-09-22 Sanyo Electric Co Ltd Vertical mosfet
EP0587176A2 (en) * 1992-09-10 1994-03-16 Kabushiki Kaisha Toshiba Gate wiring of DMOSFET

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01238174A (en) * 1988-03-18 1989-09-22 Sanyo Electric Co Ltd Vertical mosfet
EP0587176A2 (en) * 1992-09-10 1994-03-16 Kabushiki Kaisha Toshiba Gate wiring of DMOSFET
EP0587176A3 (en) * 1992-09-10 1994-04-20 Toshiba Kk
US5420450A (en) * 1992-09-10 1995-05-30 Kabushiki Kaisha Toshiba Semiconductor device having stable breakdown voltage in wiring area

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