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JPS5714238A - Connection device for synchronous circuit - Google Patents

Connection device for synchronous circuit

Info

Publication number
JPS5714238A
JPS5714238A JP8950480A JP8950480A JPS5714238A JP S5714238 A JPS5714238 A JP S5714238A JP 8950480 A JP8950480 A JP 8950480A JP 8950480 A JP8950480 A JP 8950480A JP S5714238 A JPS5714238 A JP S5714238A
Authority
JP
Japan
Prior art keywords
line
circuit
transmission
register
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8950480A
Other languages
Japanese (ja)
Other versions
JPS6133489B2 (en
Inventor
Toshihiro Kamiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8950480A priority Critical patent/JPS5714238A/en
Publication of JPS5714238A publication Critical patent/JPS5714238A/en
Publication of JPS6133489B2 publication Critical patent/JPS6133489B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To obtain a microprogram-controllable synchronous interface based upon the advice X series of CCITT by monitoring lines R and I and detecting and reporting breaking and releasing operations by making a line T controllable in reception mode, and by reading the state of the line I and making a line C directly controllable. CONSTITUTION:The read and write data path of the data register 32 of a circuit connection part 10 is provided with series-parallel conversion controlling circuit 36 for transmitted and received data. Further, an X register 34 wherein control information from a host device is written, and a transmission control circuit 37 which sends the control information written in the X register to a transmission line T is reception mode when it is connected to the line T and sends the output data of the converting circuit 36 to the transmission line in transmission mode are provided. Then, a monitoring circuit 38 is provided which detects monitoring reception lines R and I being possible, the line R having a space polarity, and a control line C from the opposite device being off, thus enabling microprogram control.
JP8950480A 1980-06-30 1980-06-30 Connection device for synchronous circuit Granted JPS5714238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8950480A JPS5714238A (en) 1980-06-30 1980-06-30 Connection device for synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8950480A JPS5714238A (en) 1980-06-30 1980-06-30 Connection device for synchronous circuit

Publications (2)

Publication Number Publication Date
JPS5714238A true JPS5714238A (en) 1982-01-25
JPS6133489B2 JPS6133489B2 (en) 1986-08-02

Family

ID=13972599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8950480A Granted JPS5714238A (en) 1980-06-30 1980-06-30 Connection device for synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5714238A (en)

Also Published As

Publication number Publication date
JPS6133489B2 (en) 1986-08-02

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