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JPS55143633A - Parallel input-output interface system - Google Patents

Parallel input-output interface system

Info

Publication number
JPS55143633A
JPS55143633A JP5106879A JP5106879A JPS55143633A JP S55143633 A JPS55143633 A JP S55143633A JP 5106879 A JP5106879 A JP 5106879A JP 5106879 A JP5106879 A JP 5106879A JP S55143633 A JPS55143633 A JP S55143633A
Authority
JP
Japan
Prior art keywords
data
instruction
line
information
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5106879A
Other languages
Japanese (ja)
Inventor
Hiroshi Takahashi
Yoshiaki Uchida
Yoshimasa Matsui
Motoyasu Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5106879A priority Critical patent/JPS55143633A/en
Publication of JPS55143633A publication Critical patent/JPS55143633A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To perform excellent data transfer with a small number of signal lines when bringing high-speed data transfer to effect between a controller and input- output device, by transferring additional information an instruction or response via a two-way data line originally for data transfer.
CONSTITUTION: Two-way data line 4 has signals lines corresponding to the number of bits of data to be transferred, and instruction line 3 consists of signal lines for sending various indications from controller 1 to input-output unit 2. Then, clock line 7 is provided which transmits the transfer direction of information to be transferred via data line 4 or instruction line 3 and the effective time of the information by using two control lines and supplies signal lines, etc., with timing. In addition to data transferred originally via data line 4, unit 1 tranfers to unit 2 information responding to the instruction or additonal information for covering the meaning of the instruction. Consequently, while the state of unit 2 is confirmed, data can effectively be transmitted.
COPYRIGHT: (C)1980,JPO&Japio
JP5106879A 1979-04-24 1979-04-24 Parallel input-output interface system Pending JPS55143633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5106879A JPS55143633A (en) 1979-04-24 1979-04-24 Parallel input-output interface system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5106879A JPS55143633A (en) 1979-04-24 1979-04-24 Parallel input-output interface system

Publications (1)

Publication Number Publication Date
JPS55143633A true JPS55143633A (en) 1980-11-10

Family

ID=12876476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5106879A Pending JPS55143633A (en) 1979-04-24 1979-04-24 Parallel input-output interface system

Country Status (1)

Country Link
JP (1) JPS55143633A (en)

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