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JPS57131146A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS57131146A
JPS57131146A JP1654381A JP1654381A JPS57131146A JP S57131146 A JPS57131146 A JP S57131146A JP 1654381 A JP1654381 A JP 1654381A JP 1654381 A JP1654381 A JP 1654381A JP S57131146 A JPS57131146 A JP S57131146A
Authority
JP
Japan
Prior art keywords
idle
processing
signal
processing device
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1654381A
Other languages
Japanese (ja)
Inventor
Shingo Yamane
Tetsuo Yano
Yoshimi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1654381A priority Critical patent/JPS57131146A/en
Publication of JPS57131146A publication Critical patent/JPS57131146A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To reduce a high-speed processing time required for a processing device, by transferring by the last timing of a transfer sequence, in case when a specific word which requires processing by both a transmitting station and a receiving station has been received. CONSTITUTION:A receiver 7 receives signals SY, S/C, 01, 02, 03, I1, I2 and IDLE in order from a transmission line 6 as shown in a figure (c), and sends them out in order of IDLE, IDLE, IDLE, I1, I2 and S/C to a transmission line 8 as shown in a figure (d). That is to say, even if the signal S/C is received by the receiver, it is stored once so that it is sent out by a timing after the signal I2. Accordingly, even if processing of a processing device 1 is not executed at a high speed as before, transfer processing of the signal 03 and S/C is not overlapped in the processing device 1.
JP1654381A 1981-02-05 1981-02-05 Data transfer system Pending JPS57131146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1654381A JPS57131146A (en) 1981-02-05 1981-02-05 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1654381A JPS57131146A (en) 1981-02-05 1981-02-05 Data transfer system

Publications (1)

Publication Number Publication Date
JPS57131146A true JPS57131146A (en) 1982-08-13

Family

ID=11919173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1654381A Pending JPS57131146A (en) 1981-02-05 1981-02-05 Data transfer system

Country Status (1)

Country Link
JP (1) JPS57131146A (en)

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