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JPS57113164A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57113164A
JPS57113164A JP18804880A JP18804880A JPS57113164A JP S57113164 A JPS57113164 A JP S57113164A JP 18804880 A JP18804880 A JP 18804880A JP 18804880 A JP18804880 A JP 18804880A JP S57113164 A JPS57113164 A JP S57113164A
Authority
JP
Japan
Prior art keywords
access
block access
information processor
data buffer
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18804880A
Other languages
Japanese (ja)
Inventor
Hiroshi Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18804880A priority Critical patent/JPS57113164A/en
Publication of JPS57113164A publication Critical patent/JPS57113164A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reduce queuing by combining parallel access with block access. CONSTITUTION:The capacity of a data buffer BF is selected corresponding to the amount of data during block access. Access to a central processor CPU via a data buffer BF makes block access function in parallel. Therefore, the efficiency of bus utilization is improved to reduce queuing due to the memory in busy.
JP18804880A 1980-12-31 1980-12-31 Information processor Pending JPS57113164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18804880A JPS57113164A (en) 1980-12-31 1980-12-31 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18804880A JPS57113164A (en) 1980-12-31 1980-12-31 Information processor

Publications (1)

Publication Number Publication Date
JPS57113164A true JPS57113164A (en) 1982-07-14

Family

ID=16216765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18804880A Pending JPS57113164A (en) 1980-12-31 1980-12-31 Information processor

Country Status (1)

Country Link
JP (1) JPS57113164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180663A (en) * 1988-01-12 1989-07-18 Fujitsu Ltd Main memory access data transfer control method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4937544A (en) * 1972-08-07 1974-04-08
JPS5127974A (en) * 1974-09-03 1976-03-09 Matsushita Electric Ind Co Ltd SHINGOKYO DOKEI KAIRO
JPS5276837A (en) * 1975-12-22 1977-06-28 Fujitsu Ltd Buffer register transfer control
JPS5368922A (en) * 1976-11-29 1978-06-19 Rca Corp Parallel access memory system
JPS5435644A (en) * 1977-08-25 1979-03-15 Hitachi Ltd Information transfer system
JPS56166568A (en) * 1980-05-27 1981-12-21 Nec Corp Information processor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4937544A (en) * 1972-08-07 1974-04-08
JPS5127974A (en) * 1974-09-03 1976-03-09 Matsushita Electric Ind Co Ltd SHINGOKYO DOKEI KAIRO
JPS5276837A (en) * 1975-12-22 1977-06-28 Fujitsu Ltd Buffer register transfer control
JPS5368922A (en) * 1976-11-29 1978-06-19 Rca Corp Parallel access memory system
JPS5435644A (en) * 1977-08-25 1979-03-15 Hitachi Ltd Information transfer system
JPS56166568A (en) * 1980-05-27 1981-12-21 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180663A (en) * 1988-01-12 1989-07-18 Fujitsu Ltd Main memory access data transfer control method

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