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JPS5697127A - Terminal system - Google Patents

Terminal system

Info

Publication number
JPS5697127A
JPS5697127A JP17233579A JP17233579A JPS5697127A JP S5697127 A JPS5697127 A JP S5697127A JP 17233579 A JP17233579 A JP 17233579A JP 17233579 A JP17233579 A JP 17233579A JP S5697127 A JPS5697127 A JP S5697127A
Authority
JP
Japan
Prior art keywords
terminal system
transmission data
channel
ram9
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17233579A
Other languages
Japanese (ja)
Other versions
JPH0143336B2 (en
Inventor
Noboru Yamamoto
Kenichi Okada
Shinji Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17233579A priority Critical patent/JPS5697127A/en
Publication of JPS5697127A publication Critical patent/JPS5697127A/en
Publication of JPH0143336B2 publication Critical patent/JPH0143336B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To obtain the terminal system without surplus and deficiency in the table area, by changing the size of the net work table and the station control block table corresponding to the actual system constitution.
CONSTITUTION: The central processing unit 1 managing the entire terminal system and the main memory 2 storing the transmission data are connected to the communication multiplexer channel 3 via the common bus C, and the channel 3 is connected to a plurality of line adaptors 4-0W4-7. This channel 3 is composed of the microprocessor 5, write-in control register 6, readout control register 7, DMA8 and RAM9 including the table area 10, and the transmission data in the main memory 8 is fetched to the buffer area in RAM9 with DAM8, the adaptors 4-0W4-7 are selected, and output is made to the terminal system as the transmission data.
COPYRIGHT: (C)1981,JPO&Japio
JP17233579A 1979-12-29 1979-12-29 Terminal system Granted JPS5697127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17233579A JPS5697127A (en) 1979-12-29 1979-12-29 Terminal system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17233579A JPS5697127A (en) 1979-12-29 1979-12-29 Terminal system

Publications (2)

Publication Number Publication Date
JPS5697127A true JPS5697127A (en) 1981-08-05
JPH0143336B2 JPH0143336B2 (en) 1989-09-20

Family

ID=15939987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17233579A Granted JPS5697127A (en) 1979-12-29 1979-12-29 Terminal system

Country Status (1)

Country Link
JP (1) JPS5697127A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58165127A (en) * 1982-03-25 1983-09-30 Nec Corp System controller
JPS59139427A (en) * 1983-01-29 1984-08-10 Fuji Electric Co Ltd information processing equipment
JPS6188361A (en) * 1984-10-01 1986-05-06 サンドストランド・データ・コントロール・インコーポレーテツド Avionic system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58165127A (en) * 1982-03-25 1983-09-30 Nec Corp System controller
JPS59139427A (en) * 1983-01-29 1984-08-10 Fuji Electric Co Ltd information processing equipment
JPS6188361A (en) * 1984-10-01 1986-05-06 サンドストランド・データ・コントロール・インコーポレーテツド Avionic system

Also Published As

Publication number Publication date
JPH0143336B2 (en) 1989-09-20

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