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JPS57207943A - Input-output controller equipped with built-in buffer memory - Google Patents

Input-output controller equipped with built-in buffer memory

Info

Publication number
JPS57207943A
JPS57207943A JP56092958A JP9295881A JPS57207943A JP S57207943 A JPS57207943 A JP S57207943A JP 56092958 A JP56092958 A JP 56092958A JP 9295881 A JP9295881 A JP 9295881A JP S57207943 A JPS57207943 A JP S57207943A
Authority
JP
Japan
Prior art keywords
data
buffer memory
built
input
output controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56092958A
Other languages
Japanese (ja)
Inventor
Kenichi Hanabe
Hiroyuki Omura
Yoshihiko Kitamikado
Isamu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56092958A priority Critical patent/JPS57207943A/en
Publication of JPS57207943A publication Critical patent/JPS57207943A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To perform data transfer between lower rank devices which operate asynchronously and block multiplex transfer in a communication system which accumulates and exchanges data, by using an input-output controller equipped with a built-in buffer memory in the system. CONSTITUTION:When a fixed amount of data is read from a communication controler 5 and the data are accumulated in a buffer memory 35, the data are transferred to a file memory 4 through a file memory interface circuit 32. When the data are delivered to an output line B, the data are read from the file memory 4, temporarily accumulated in the buffer memory 35, and then, transferred to a communication controller 33. Since the buffer memory has plural faces, block multiplex transfers are performed by utilizing the accessing time.
JP56092958A 1981-06-18 1981-06-18 Input-output controller equipped with built-in buffer memory Pending JPS57207943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56092958A JPS57207943A (en) 1981-06-18 1981-06-18 Input-output controller equipped with built-in buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56092958A JPS57207943A (en) 1981-06-18 1981-06-18 Input-output controller equipped with built-in buffer memory

Publications (1)

Publication Number Publication Date
JPS57207943A true JPS57207943A (en) 1982-12-20

Family

ID=14068955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56092958A Pending JPS57207943A (en) 1981-06-18 1981-06-18 Input-output controller equipped with built-in buffer memory

Country Status (1)

Country Link
JP (1) JPS57207943A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0340057A (en) * 1989-07-06 1991-02-20 Pioneer Electron Corp Data transfer device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0340057A (en) * 1989-07-06 1991-02-20 Pioneer Electron Corp Data transfer device

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