JPS58165127A - System controller - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware such as a cable for the communication between devices, by providing a system controller which controls the data transmission to another data processing device on the basis of the transmission request from optional one of amny data processing devices. CONSTITUTION:Plural data processing devices 30-33 are connected to a system controller 20 by communication busses 50-53 and memory access busses 60-63, and the controller 20 is connected to a storage device 10 by a memory access buss 4. The controller 20 has an interface availability indicating circuit, a communication request holding circuit, and a transmission controlling circuit for every processing device and accepts the communication request from one processing device to another and controls the transmission of communication data to one or plural prescribed processing devices.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system control device 411 having interfaces with a plurality of devices and for performing overconfidence between devices.

Conventionally, this type of information 4611 device has prepared a communication path between each device and has a means for controlling overconfidence within each device, as shown in Fig. M1.

The information processing device shown in FIG. 1 includes a storage device 10, data processing devices 30 to 33, and memory access paths 40 to 43.
and inter-device overconfidence paths 401 to 423.

FIGS. 2(1) and 2(b) are block diagrams showing the overconfidence control section of the data processing apparatus 30 shown in FIG. The data processing devices 31 to 33 also have the same communication control section as shown in FIGS. 2(a) and 2(b). FIG. 2(a) Fi transmitting section FIG. 2 0)) shows the receiving section.

The communication control unit shown in FIGS. 2(Jl) and (b) includes a transmission data register 101, a transmission request circuit 102, a destination device number decoding circuit 105, an ink 731-space validity instruction circuit 200 to 202, Transmission control circuits 240 to 24
2, reception control circuits 251 to 262, reception data register 103, and reception display circuit 104.

Figure 3) is the format of communication data used in the information processing device shown in Figure 1.One communication data consists of a destination device number A, a source device number B, and a communication parameter C. There is. FIG. 3(a) is a diagram showing the relationship between the destination device number A1 shown in FIG. 3(a), the source device number B shown in FIG. 3, and the data processing device shown in FIG.

The operation at the time of transmission will be described below using transmission from the data processing device 30 to the data processing device 32 as an example.

The data processing device 30 has “destination device number At”2@,
The communication data with the source device number B set to °O' is set in the transmission data register 01, and a transmission request is instructed to the transmission request circuit 102.

□ Source device number and destination device number decoding circuit 10
If the interface ■□ validity indication circuit 201 indicates valid □, the transmission control circuit 208 sends a communication request together with the communication data to the 5 communication path 402.

Next, an example in which the data processing device 30 receives communication from the data processing device 32 will be described below regarding the operation at the time of reception.

Communications between data processing devices 32 are sent over one communications path 402'. If the interface valid indication circuit 201 indicates that the interface is invalid, the reception control circuit 25
9.260 communications from data processing device 32 are ignored. If the interface validity indication circuit 201 indicates that the interface is valid, the reception control circuit 259.26
0 enables communication from the data processing device 32, sets communication data in the reception data register 03, and displays reception on the reception display circuit 104.

Next, the overall sequence of 5 communications will be explained.

1 The data processing device 30 applies a lock before starting communication, and after the lock is successful, sends communication data I to the data processing device □ 32. Reception display circuit 1041・
.

The data processing device 32 indicates that the communication data has been received.
When recognized, the data processing device 32 decodes the communication parameter C of the communication data set in the received data register 03, and performs the necessary processing based on the instruction of this communication parameter C. The data processing device 32 terminates the processing. rear,
The transmission source device number B is sent to the survey data processing device 30 as communication data indicating the end of processing. The data processing device 30 releases the lock after receiving the communication data for which processing has been completed.

Next, configuration control will be explained.

An example will be described in which the data processing device 30 disconnects the data processing device 33 while data processing devices 3-0 to 33 are processing data.

The data processing device 30 has an interface enablement instruction circuit 202 for the data processing device 33 provided within the device itself.
indicates invalidity, and instructs the data processing devices a1 and 32 to disconnect the data processing device 33 by communication.

The data processing devices 31 and 32 that received the scissor communication each send 7 g of ink to the data processing device 33 in their own devices.
-Set the valid instruction circuit to indicate invalid, and send a processing end notification to the data processing device 30 respectively.

Since the data processing device 30 receives the completion of processing from the data processing devices 31 and 32, the data processing device 33
It is a good thing that they are separated.

As is clear from the above explanation of the configuration and operation, in the conventional information processing device configuration, as the number of data processing devices increases, the communication paths between each device and the amount of circuitry for communication are extremely large. However, the disadvantage is that it becomes complicated to control the interface between each device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a system control device that can reduce the amount of rounded cables and hardware for communication between devices in a multiplex processor system, and easily control the interface between devices. There is a thing called K.

The system control device of the present invention includes an interface validity indication means for indicating whether or not the interface is valid corresponding to the am device, and an interface validity indication means from the device indicating that the ink7g-based voice effect indication means is valid. a holding means for holding a communication request and data; and a holding means for holding a communication request and data; The device includes communication exit means for sending communication to all devices that are not connected to the device.

That is, the system control device of the present invention provides a system control device having interfaces with a plurality of devices, an interface validity indicator "stage indicating validity/invalidity of the interface corresponding to each device, and the interface validity indication means indicating validity. means for holding communication requests and data from devices; The apparatus is constructed with means for transmitting overconfidence to all the moat equipment.
゛ □ Next, embodiments of the present invention will be described in detail I11 with reference to the drawings.゛Figure 4 shows the present invention in six multiplex systems.
There is 1"1-t'6-°1"°"'.

Information processing device Hiro, storage device 107, system control device 20, and data II & field devices 30 to 33 shown in No. 4-
, a memory access bus 4 from the system control device to the storage device, communication buses 50 to 53, and memory access buses 60 to 63 from each data processing device.

5E is a block diagram showing details of the system control device of the present invention.

The system control device shown in FIG. Request control circuit 21, communication data holding circuit 22, destination device □ number decoding circuit xosi, communication path 50~
53. 6 is a diagram showing in detail a part of the communication system of the data processing device 30.

Data processing value! '31.32.33 also has a similar circuit configuration. '#! The data 4611 device shown in FIG. 6 is the reception display circuit 10.
4, reception data register 103, and transmission request circuit 10
2 and a transmission data register 101.

FIG. 7(a) is a format showing an example of communication data used in the information processing device shown in FIG. 4. It is composed of the parameters C' and C'.

FIG. 7(b) shows the destination device number A' shown in FIG. 7(a).
This is a relationship diagram showing the correspondence between the transmission source device number B' and the data processing devices 30 to 33 shown in FIG. 'The data processing device 30 sets the communication data with the destination device number A' as 4 degrees and the source device number B' as 0 degrees into the transmission data register 101, and the transmission request circuit 102 issues a transmission request. The operation when this is performed will be explained below.
”-.

Interface valid indication circuit 200゜201 as a condition
．． Assume that 203 indicates valid and interface valid indication circuit 202 indicates invalid.

The communication data and communication request of the data processing value fIt30 are sent to the system control device 20 via the communication path 50.

Since the interface 7JL-base enable instruction link 200 indicates enable, the interface gate circuit 210゜220#i
0 communication request holding circuit 23 that imports the contents of the communication path 50
A communication request is held at 0, and communication data is held at □ communication data holding circuit 22. Since the destination device number M' is 4 degrees, the destination device number de;-F circuit 105 sends a signal to the transmission control circuit 240 241.242.243 to disable the validity of the interface. send. The transmission control circuit 240#'i1 communication request holding circuit 23''O holds the overconfidence request and does not transmit it to the data processing device 30.

Indicates the validity of the communication request retention cycle 3! , 2$3 does not hold a communication request, and the destination device honor code code circuit 10
The devices send data to the ninth data processing device 31, 33, each indicating validity. The transmission control circuit 242 does not transmit the data 4611 to the device 32 because the ink 7m-space validity instruction circuit 202 indicates invalidity.

Ru.

The information processing device shown in FIG. 8 includes a storage device 10.11, system control devices 12A and 2B, and data processing devices 30 to
33, system control devices 2A, 2B, and storage device 10.
11, data processing devices 30 to 33, data buses 70 to 73 to system control devices 2A and 2B, and intermediate system control devices 2A and 2B.
Includes 7g of Misaki ink between B and 6.

The system control device shown in FIG.

FIG. 2 is a block diagram showing details of 2B.

In the second embodiment shown in FIG. 9, a dedicated path for one communication is not used, and an address bus for memory access is used as the transmission data bus, and a cache: & match processing bus is used as the affection data bus. In this embodiment, the path is set as the communication request path and the communication request path is set as the communication request path.

This is for indicating the validity/invalidity of the interface between the System Control Equipment Co., Ltd. and the interface validation circuit 200 to 203.2OA, 20BIt, and the interface validation/water circuit 20A, 20alFiv step 5 control device shown in FIG. M9. Interface gate circuit 210-2
13 ・220-22 B, 21A.

door Calyx 22mm, 23mm, 924mm, 21B, 22B.

23B and '24B are interface gate circuits that control the interface (according to instructions from the interface 7 aa-jC valid indicating circuit). The refresher code 1 holding circuits 230' to 233' hold communication requests as one request code. Address holding circuit 260-2i
s S ll1s When overconfidence occurs, overconfidence data is held.

In addition, Ks switching circuits 81 to 84, request holding system circuits 88 and 811, and address communication data holding circuits 8
7,88 and the destination device number fH-1'11111G!
! Mmm, 10! ! Bfi@control circuit 240-2462. Access control circuit 26m.

Contains 25B.

Interface valid indication circuit 200.2OA.

The communication operation from the data processing device 30 to the data processing device 33 when 20B and 203 indicate validity will be described below.

The data processing device 3o sets the destination device number A' to 3 degrees.

Communication data with source device number B' as °0°.

A request code for a communication request is sent to the data bus 7o. Since the ink 7 process validity indication circuit 200 indicates validity, the communication request request code is held in the request code holding circuit 2.30', and the communication data is held in the address holding circuit 260. Switching circuit 81.8
3 are selected from the request code holding circuit 230' and the address holding circuit 260, respectively.

Since the interface valid indication circuits 20A and 20B) indicate that IN is valid, the outputs of the switching circuits 81 and 83 are sent to the system control device 2BK, and the request holding control circuit 8
6 and is held in the address communication data holding circuit 88. The output of the switching circuit 8168.3 is simultaneously the request holding control circuit 8! S and address are also held in the communication data holding circuit 88. Destination equipment number decoding circuit 105A, 105
The destination device number A' is decoded at B, and as a result,
Among the transmission control circuits 240 to 243, the transmission control circuit 24
Only 3 is valid.

Since the interface/ace validity indication circuit 203 indicates validity, one communication data and a communication request are sent to the data bus 53. Data processing device 33 lines.

Data bus! An overconfidence data communication request can be received from s3.

Next, configuration control will be explained.

When the data processing device 30 disconnects the data processing device 31, the data processing device 31, the data processing device 30.
3! ! , can be separated from 3m.

However, in the configuration of the present invention shown in FIG. 4, only N pieces are required.

Therefore, this method is effective when the number of devices performing inter-device communication is three or more.

The system control device of the present invention has the advantage of reducing the communication path and amount of hardware for inter-device communication, and easily controlling the interface between each device.

[Brief explanation of the drawing]

FIG. 1 is an overall system configuration diagram showing an example of a conventional information processing device, FIG. 2 is a block diagram showing details of the communication control section of the data processing device 20 shown in FIG. 1 is a format showing an example of communication data used in the information layer device shown in FIG. 5 is a block diagram showing in detail the system control device 2 shown in FIG. 1, which is an embodiment of the present invention; FIG. The block diagram shown in FIG. 7 shows an example of communication data used in the information layer device shown in the 41st QK, and FIG. System configuration diagram shown,
FIG. 9 is a block diagram showing in detail the system control devices mA, 2B shown in FIG. 8, which is another embodiment of the present invention. 10.11-°...Storage device, 20.2A, 2B.
...System control device, 21 ... Communication request control circuit, 22 ... Communication data holding circuit, 3
0~33・Old data management equipment, 81~84・・・・
...Switching circuit, 85°86...Request holding control circuit, 87.88...Address communication data holding circuit, 101°°°...Transmission data register, 1
02""...Transmission request circuit, 103...Reception data register, 104---Reception display circuit,
205.105A, 105B - Destination device number decoding times - 1200 to 203.20 people, 20B〆... Inter-nasal valid indication circuit, 210 to
213.220~223.21A~24B-...
Interface gate circuit%230-233...
・・Overconfidence request time keeping circuit, 23G'~233I・・・・
...Request code holding circuit, 240-243---
---Transmission control circuit, 250-255--Reception control circuit, 260-263--Address holding circuit, 40-43, 4.60-63...Memory access Paths 1401-423 Old... Inter-device communication path, 50-53... Communication path, 6... Control interface, 70-73... Data bus, A, A '...Destination device number, B, B/
・・・・・・Sender device number %C,C/ ・・・・
...Communication parameters. Prefecture l Diagram (α) Leather 3 Diagram #m! 1

Claims (1)

[Claims] an interface validity indication means for indicating whether or not the interface is valid corresponding to the arguend device; and a holding means for retaining communication requests and data from the device for which the interface validity indication means indicates that the interface is valid; The communication request causes the interface to be sent to the device group indicated by the data, and the communication is made to all the devices that have not sent the communication request although the instruction means indicates that the device is valid. A system control device comprising communication sending means for sending out.