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JPS567161A - Memory interface device - Google Patents

Memory interface device

Info

Publication number
JPS567161A
JPS567161A JP8081779A JP8081779A JPS567161A JP S567161 A JPS567161 A JP S567161A JP 8081779 A JP8081779 A JP 8081779A JP 8081779 A JP8081779 A JP 8081779A JP S567161 A JPS567161 A JP S567161A
Authority
JP
Japan
Prior art keywords
memory
signal
line
arbiter
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8081779A
Other languages
Japanese (ja)
Other versions
JPS6125178B2 (en
Inventor
Tadaaki Bando
Yasushi Fukunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8081779A priority Critical patent/JPS567161A/en
Publication of JPS567161A publication Critical patent/JPS567161A/en
Publication of JPS6125178B2 publication Critical patent/JPS6125178B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To decrease the number of interface lines by selecting the memory start signal, detecting the memory read request and then storing the selection signal in the order of first-in and first-out FIFO for control.
CONSTITUTION: Arbiter 12 receives memory use request 14 from plural processors PC and then selects one of them to deliver selection signal 15. The selected PC is connected to the memory via selectors 17 and 18 each to give start to the memory via memory start line 22. Selector 17 selects the read/line command given from each PC. And the selection result is transmitted to the memory via line 5 and also used as the writing condition signal to FIFO buffer 13. Only when the output from selector 17 among those selected by arbiter 12 is memory read request, the output is written into buffer 13 and then delivered in sequence through the control. Thus the memory bus is used in time-division to decrease the number of the necessary lines.
COPYRIGHT: (C)1981,JPO&Japio
JP8081779A 1979-06-28 1979-06-28 Memory interface device Granted JPS567161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8081779A JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8081779A JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Publications (2)

Publication Number Publication Date
JPS567161A true JPS567161A (en) 1981-01-24
JPS6125178B2 JPS6125178B2 (en) 1986-06-14

Family

ID=13728996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8081779A Granted JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Country Status (1)

Country Link
JP (1) JPS567161A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143658A (en) * 1981-03-02 1982-09-04 Nec Corp Microcomputer compounding system
JPS58114155A (en) * 1981-12-23 1983-07-07 シ−メンス・アクチエンゲゼルシヤフト Data processor
JPS61150054A (en) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド Data processor
JPS63257051A (en) * 1987-04-15 1988-10-24 Hitachi Ltd Multicomputer system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221736A (en) * 1975-08-08 1977-02-18 Western Electric Co Multiprocessor processor and device for poling memory request

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221736A (en) * 1975-08-08 1977-02-18 Western Electric Co Multiprocessor processor and device for poling memory request

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143658A (en) * 1981-03-02 1982-09-04 Nec Corp Microcomputer compounding system
JPS58114155A (en) * 1981-12-23 1983-07-07 シ−メンス・アクチエンゲゼルシヤフト Data processor
JPS61150054A (en) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド Data processor
JPS63257051A (en) * 1987-04-15 1988-10-24 Hitachi Ltd Multicomputer system
JPH054711B2 (en) * 1987-04-15 1993-01-20 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6125178B2 (en) 1986-06-14

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