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JPS5654560A - Memory system - Google Patents

Memory system

Info

Publication number
JPS5654560A
JPS5654560A JP13149279A JP13149279A JPS5654560A JP S5654560 A JPS5654560 A JP S5654560A JP 13149279 A JP13149279 A JP 13149279A JP 13149279 A JP13149279 A JP 13149279A JP S5654560 A JPS5654560 A JP S5654560A
Authority
JP
Japan
Prior art keywords
memory
file
transfer
controller
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13149279A
Other languages
Japanese (ja)
Inventor
Kenichi Hanabe
Takashi Kawade
Toshio Suhara
Kunio Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13149279A priority Critical patent/JPS5654560A/en
Publication of JPS5654560A publication Critical patent/JPS5654560A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To improve the processing performance of a system by displaying the transfer performance of a file memory at its maximum by performing transfer between a random buffer memory and a random file memory freely when the file memory is empty.
CONSTITUTION: Buffer memories 21...24 and file memories 26 and 27 are connected to common controller 25 and brought under its control. To transfer data from memory 21 to file memory 26, a transfer request is sent out of memory 21 to controller 25. On receiving this request, controller 25 sends the command to memory 26 in the FIFO form. Consequently, memory 26 actuates memory 21, which set the access address in RAM30 and the number of words to be transferred to internal interface circuit 34 and informs memory 26 of actuation completion. Then, the data are transferred and while the transfer performance of file memories can be displayed to the maximum, the processing performance of the system can be improved.
COPYRIGHT: (C)1981,JPO&Japio
JP13149279A 1979-10-12 1979-10-12 Memory system Pending JPS5654560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13149279A JPS5654560A (en) 1979-10-12 1979-10-12 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13149279A JPS5654560A (en) 1979-10-12 1979-10-12 Memory system

Publications (1)

Publication Number Publication Date
JPS5654560A true JPS5654560A (en) 1981-05-14

Family

ID=15059253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13149279A Pending JPS5654560A (en) 1979-10-12 1979-10-12 Memory system

Country Status (1)

Country Link
JP (1) JPS5654560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60156159A (en) * 1984-01-25 1985-08-16 Hitachi Ltd magnetic bubble memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60156159A (en) * 1984-01-25 1985-08-16 Hitachi Ltd magnetic bubble memory device
JPH0544755B2 (en) * 1984-01-25 1993-07-07 Hitachi Ltd

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