JPS56118132A - Dma data transferring system - Google Patents
Dma data transferring systemInfo
- Publication number
- JPS56118132A JPS56118132A JP2243180A JP2243180A JPS56118132A JP S56118132 A JPS56118132 A JP S56118132A JP 2243180 A JP2243180 A JP 2243180A JP 2243180 A JP2243180 A JP 2243180A JP S56118132 A JPS56118132 A JP S56118132A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- address
- gate
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To enable to freely transfer the data and address to an arbitrary address, by temporarily storing the data and address and executing the transfer with the permission signal to the transfer request, in the DMA transfer from the peripheral device of computer. CONSTITUTION:The data and address from the peripheral device of a computer are written in the first-in/first-out (FIFO) 1 and 2 in synchronizing with the shift-in signal, the data end bit signal added with the final data is fed to FIFO2 and also to the gate 3, to invert the output of FF4, and the DMA request signal is inputted to CPU via the gate 6 and 7. When the permission signal from CPU is fed to the frequency-division circuit 9 via the gate 8, the DMA clock input is inenabling state and the write signal is inputted to CPU via the gate (driver) 10 and bus 7, and the data and address signal are continuously read out by supplying the shift-out signal to FIFO 1, 2, and they are written in the main memory of CPU via the bus 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2243180A JPS56118132A (en) | 1980-02-25 | 1980-02-25 | Dma data transferring system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2243180A JPS56118132A (en) | 1980-02-25 | 1980-02-25 | Dma data transferring system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56118132A true JPS56118132A (en) | 1981-09-17 |
Family
ID=12082498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2243180A Pending JPS56118132A (en) | 1980-02-25 | 1980-02-25 | Dma data transferring system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56118132A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914033A (en) * | 1982-07-14 | 1984-01-24 | Nec Corp | Peripheral control device |
| JPS61286955A (en) * | 1985-06-13 | 1986-12-17 | Yokogawa Medical Syst Ltd | Method for transferring data |
| JPS6273362A (en) * | 1985-09-26 | 1987-04-04 | Fujitsu Ltd | Demand transfer circuit |
-
1980
- 1980-02-25 JP JP2243180A patent/JPS56118132A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914033A (en) * | 1982-07-14 | 1984-01-24 | Nec Corp | Peripheral control device |
| JPS61286955A (en) * | 1985-06-13 | 1986-12-17 | Yokogawa Medical Syst Ltd | Method for transferring data |
| JPS6273362A (en) * | 1985-09-26 | 1987-04-04 | Fujitsu Ltd | Demand transfer circuit |
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