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JPS5578346A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5578346A
JPS5578346A JP15056378A JP15056378A JPS5578346A JP S5578346 A JPS5578346 A JP S5578346A JP 15056378 A JP15056378 A JP 15056378A JP 15056378 A JP15056378 A JP 15056378A JP S5578346 A JPS5578346 A JP S5578346A
Authority
JP
Japan
Prior art keywords
address
micro instruction
current cycle
micro
instruction executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15056378A
Other languages
Japanese (ja)
Inventor
Kiyoshi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15056378A priority Critical patent/JPS5578346A/en
Publication of JPS5578346A publication Critical patent/JPS5578346A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce considerably the capacity of a ROM by sending one of the output of a register, which sets a branch address, and the address signal of a micro instruction executed in the current cycle to the first or the second ROM as address information.
CONSTITUTION: Micro instructions are read from microprogram memories ROM1 and ROM2, which store micro instructions, respectively, and one micro instruction read by select signal 104 determined by the micro instruction executed in the current cycle is selected. In this case, one of the output of register REG and the address signal of the micro instruction executed in the current cycle is selected as address information by selector SEL1 or SEL2 dependently upon register REG which sets a branch address. Then, information selected by selector SEL1 or SEL2 is supplied to ROM1 or ROM2. As a result, the capacity of the microprogram memory can be reduced considerably.
COPYRIGHT: (C)1980,JPO&Japio
JP15056378A 1978-12-07 1978-12-07 Microprogram control unit Pending JPS5578346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15056378A JPS5578346A (en) 1978-12-07 1978-12-07 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15056378A JPS5578346A (en) 1978-12-07 1978-12-07 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5578346A true JPS5578346A (en) 1980-06-12

Family

ID=15499605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15056378A Pending JPS5578346A (en) 1978-12-07 1978-12-07 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5578346A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5872249A (en) * 1981-10-27 1983-04-30 Mitsubishi Electric Corp Controlling device for microprogram sequence

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5872249A (en) * 1981-10-27 1983-04-30 Mitsubishi Electric Corp Controlling device for microprogram sequence
JPH0115091B2 (en) * 1981-10-27 1989-03-15 Mitsubishi Electric Corp

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