JPS55143067A - Manufacture of dual insulated gate field effect transistor - Google Patents
Manufacture of dual insulated gate field effect transistorInfo
- Publication number
- JPS55143067A JPS55143067A JP15540978A JP15540978A JPS55143067A JP S55143067 A JPS55143067 A JP S55143067A JP 15540978 A JP15540978 A JP 15540978A JP 15540978 A JP15540978 A JP 15540978A JP S55143067 A JPS55143067 A JP S55143067A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- region
- polycrystalline
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To reduce feed back capacitance by a method wherein an oxide film is perfolated to have two gate oxide films in a separated distance on a substrate and diffusion of impurity is performed through a polycrystalline film formed selectively as an opening and the gate oxide film. CONSTITUTION:A thick oxide film 2 on a p<->-type silicon substrate 1 is bored and gate oxide films 2G1, 2G2 are formed. At a region apart from these and in a specified distance and a region between them the oxide film 2 is perforated at a specified region, and a polycrystalline Si film 3 is formed selectively on these openings and gate oxide film regions. Next thereto n<+>-layers 4S, 5, 4D are formed by diffusion of phosphorus through the polycrystalline Si film 3. Next thereto they are covered with an oxide film, and electrode is built through the opening provided on it. By this constitution two FETs can be fabricated to occupy a small area with self- alignment action, and since two gate electrodes and region do not overlap, capacitance between the drain electrode 4D of the second FET and the substrate and feed back capacitance are extremely reduced, and stable operation is performed by eliminating self-oscillation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15540978A JPS55143067A (en) | 1978-12-13 | 1978-12-13 | Manufacture of dual insulated gate field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15540978A JPS55143067A (en) | 1978-12-13 | 1978-12-13 | Manufacture of dual insulated gate field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55143067A true JPS55143067A (en) | 1980-11-08 |
Family
ID=15605344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15540978A Pending JPS55143067A (en) | 1978-12-13 | 1978-12-13 | Manufacture of dual insulated gate field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55143067A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4932474A (en) * | 1972-07-24 | 1974-03-25 | ||
JPS501988A (en) * | 1973-05-11 | 1975-01-10 |
-
1978
- 1978-12-13 JP JP15540978A patent/JPS55143067A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4932474A (en) * | 1972-07-24 | 1974-03-25 | ||
JPS501988A (en) * | 1973-05-11 | 1975-01-10 |
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