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JPS5497384A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5497384A
JPS5497384A JP492378A JP492378A JPS5497384A JP S5497384 A JPS5497384 A JP S5497384A JP 492378 A JP492378 A JP 492378A JP 492378 A JP492378 A JP 492378A JP S5497384 A JPS5497384 A JP S5497384A
Authority
JP
Japan
Prior art keywords
type
region
film
substrate
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP492378A
Other languages
Japanese (ja)
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP492378A priority Critical patent/JPS5497384A/en
Publication of JPS5497384A publication Critical patent/JPS5497384A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a CMOS element of a high integration degree by providing a poly-crystal Si film onto an insulating film at the circumference of a unidirectionally- conductive FET formed on the main surface of a semiconductor substrate and by connecting electrically source regions of two FETs each other after forming the reversely-conductive channel type FET on the Si film. CONSTITUTION:In either region of the surface of P-type Si substrate 101, N-type drain region 102 and N-type source region 103 are diffusion-formed and onto substrate 101 between both the region, gate SiO2 film 104 and poly-crystal Si gate electrode 105 are adhered, thereby constituting a N-channel MOSFET. In the other region of the surface of substrate 101, P<+>-type region 106 is diffusion-formed and covered with thick SiO2 film 107, on which N-type poly-crystal Si film 108 is deposited. Then, P-type drain region 109 and P-type source region 110 are diffusion formed at both terminals of this film 108 and gate SiO2 film 111 straddling on both the regions and Al gate electrode 112 are provided, thereby obtaining a P-channel MOSFET. Next, respective source regions are connected through Al electrode 113.
JP492378A 1978-01-19 1978-01-19 Semiconductor device Pending JPS5497384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP492378A JPS5497384A (en) 1978-01-19 1978-01-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP492378A JPS5497384A (en) 1978-01-19 1978-01-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5497384A true JPS5497384A (en) 1979-08-01

Family

ID=11597122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP492378A Pending JPS5497384A (en) 1978-01-19 1978-01-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5497384A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442448A (en) * 1979-10-26 1984-04-10 Seiko Instruments & Electronics Ltd. Logic integrated circuit device
JPS60220960A (en) * 1984-01-24 1985-11-05 テキサス　インスツルメンツ　インコ−ポレイテツド Cmos integrated circuit device
JPS63142849A (en) * 1986-12-05 1988-06-15 Matsushita Electronics Corp Semiconductor device and its manufacturing method
US4754314A (en) * 1984-01-24 1988-06-28 Texas Instruments Incorporated Split-level CMOS
US4777147A (en) * 1987-01-28 1988-10-11 Texas Instruments Incorporated Forming a split-level CMOS device
US4947227A (en) * 1985-09-16 1990-08-07 Texas Instruments, Incorporated Latch-up resistant CMOS structure
JP2006148141A (en) * 2004-11-24 2006-06-08 Taiwan Semiconductor Manufacturing Co Ltd Self-aligned double gate device and method for forming the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442448A (en) * 1979-10-26 1984-04-10 Seiko Instruments & Electronics Ltd. Logic integrated circuit device
JPS60220960A (en) * 1984-01-24 1985-11-05 テキサス　インスツルメンツ　インコ−ポレイテツド Cmos integrated circuit device
US4754314A (en) * 1984-01-24 1988-06-28 Texas Instruments Incorporated Split-level CMOS
US4947227A (en) * 1985-09-16 1990-08-07 Texas Instruments, Incorporated Latch-up resistant CMOS structure
JPS63142849A (en) * 1986-12-05 1988-06-15 Matsushita Electronics Corp Semiconductor device and its manufacturing method
US4777147A (en) * 1987-01-28 1988-10-11 Texas Instruments Incorporated Forming a split-level CMOS device
JP2006148141A (en) * 2004-11-24 2006-06-08 Taiwan Semiconductor Manufacturing Co Ltd Self-aligned double gate device and method for forming the same

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