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JPS5486242A - Nor type decoder circuit - Google Patents

Nor type decoder circuit

Info

Publication number
JPS5486242A
JPS5486242A JP15408277A JP15408277A JPS5486242A JP S5486242 A JPS5486242 A JP S5486242A JP 15408277 A JP15408277 A JP 15408277A JP 15408277 A JP15408277 A JP 15408277A JP S5486242 A JPS5486242 A JP S5486242A
Authority
JP
Japan
Prior art keywords
circuit
decoder circuit
type decoder
power
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15408277A
Other languages
Japanese (ja)
Inventor
Sumio Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15408277A priority Critical patent/JPS5486242A/en
Publication of JPS5486242A publication Critical patent/JPS5486242A/en
Pending legal-status Critical Current

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  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To reduce the power consumption of a NOR type decoder circuit by using a differential inverter circuit and by supplying its output to the power terminal of the NOR type decoder circuit.
CONSTITUTION: With an address signal set to B0="1", the output of inverter circuit 2a is "1", that is, power voltage Vcc is supplied to NOR type decoder circuit 1a and the output of inverter circuit 2a is "0", that is, power terminal 3b of NOR type decoder circuit 1b is grounded. In this way, only one decoder circuit 1a operates and the other decoder circuit 1b which does not operate consumes no power. With B0 equal to "0", on the contrary, only circuit 1b operates and circuit 1a consumes no power, Therefore, the power consumption of either NOR type decoder in a standby state can be made zero.
COPYRIGHT: (C)1979,JPO&Japio
JP15408277A 1977-12-21 1977-12-21 Nor type decoder circuit Pending JPS5486242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15408277A JPS5486242A (en) 1977-12-21 1977-12-21 Nor type decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15408277A JPS5486242A (en) 1977-12-21 1977-12-21 Nor type decoder circuit

Publications (1)

Publication Number Publication Date
JPS5486242A true JPS5486242A (en) 1979-07-09

Family

ID=15576487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15408277A Pending JPS5486242A (en) 1977-12-21 1977-12-21 Nor type decoder circuit

Country Status (1)

Country Link
JP (1) JPS5486242A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741736A (en) * 1980-08-26 1982-03-09 Fujitsu Ltd Decoder circuit
JPS5752234A (en) * 1980-09-12 1982-03-27 Pioneer Electronic Corp Logical operation circuit
JPS5765927A (en) * 1980-10-13 1982-04-21 Hitachi Ltd Logical operation circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741736A (en) * 1980-08-26 1982-03-09 Fujitsu Ltd Decoder circuit
JPS5752234A (en) * 1980-09-12 1982-03-27 Pioneer Electronic Corp Logical operation circuit
JPS5765927A (en) * 1980-10-13 1982-04-21 Hitachi Ltd Logical operation circuit

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