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JPS5591861A - Cmos logic circuit - Google Patents

Cmos logic circuit

Info

Publication number
JPS5591861A
JPS5591861A JP16229478A JP16229478A JPS5591861A JP S5591861 A JPS5591861 A JP S5591861A JP 16229478 A JP16229478 A JP 16229478A JP 16229478 A JP16229478 A JP 16229478A JP S5591861 A JPS5591861 A JP S5591861A
Authority
JP
Japan
Prior art keywords
cmos logic
power supply
logic circuit
level shift
shift means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16229478A
Other languages
Japanese (ja)
Inventor
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16229478A priority Critical patent/JPS5591861A/en
Publication of JPS5591861A publication Critical patent/JPS5591861A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce power consumption by providing a level shift means between VDD electrode of a CMOS logic circit and No.1 power supply, or between VSS electrode and No.2 power supply. CONSTITUTION:A CMOS logic circuit consists of No.1 level shift means provided between source electrode 12 of N-MOS-TR in the CMOS logic circuit and No.2 power supply terminal 3, and No.2 level shift means provided between source electrode 22 of P-MOS-TR 20 and No.1 power supply terminal 4. Since the logic amplitude at output 2 is made smaller compared with the conventional device. Power consumption is thus reduced.
JP16229478A 1978-12-29 1978-12-29 Cmos logic circuit Pending JPS5591861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16229478A JPS5591861A (en) 1978-12-29 1978-12-29 Cmos logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16229478A JPS5591861A (en) 1978-12-29 1978-12-29 Cmos logic circuit

Publications (1)

Publication Number Publication Date
JPS5591861A true JPS5591861A (en) 1980-07-11

Family

ID=15751747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16229478A Pending JPS5591861A (en) 1978-12-29 1978-12-29 Cmos logic circuit

Country Status (1)

Country Link
JP (1) JPS5591861A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612461A (en) * 1984-02-09 1986-09-16 Motorola, Inc. High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting
US4837460A (en) * 1983-02-21 1989-06-06 Kabushiki Kaisha Toshiba Complementary MOS circuit having decreased parasitic capacitance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837460A (en) * 1983-02-21 1989-06-06 Kabushiki Kaisha Toshiba Complementary MOS circuit having decreased parasitic capacitance
US4612461A (en) * 1984-02-09 1986-09-16 Motorola, Inc. High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting

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