[go: up one dir, main page]

JPS5534577A - Clock driver circuit - Google Patents

Clock driver circuit

Info

Publication number
JPS5534577A
JPS5534577A JP10783978A JP10783978A JPS5534577A JP S5534577 A JPS5534577 A JP S5534577A JP 10783978 A JP10783978 A JP 10783978A JP 10783978 A JP10783978 A JP 10783978A JP S5534577 A JPS5534577 A JP S5534577A
Authority
JP
Japan
Prior art keywords
logic
output
driver circuit
inverters
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10783978A
Other languages
Japanese (ja)
Inventor
Takahiro Sagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10783978A priority Critical patent/JPS5534577A/en
Publication of JPS5534577A publication Critical patent/JPS5534577A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To shorten the rise time and decay time for pulses, enlarge output and reduce power consumption in a clock driver circuit by constituting the clock driver circuit by means of two inverter circuits and one transistor. CONSTITUTION:A clock input signal is entered into input terminal 1 and, when the input sides of inverters 5 and 6 are logic ''1'', the inside output transistors of inverters are connected and the output sides become logic ''0''. Therefore, transistor 7 is disconnected and output terminal 4 becomes logic ''0''. In case of no input clock signal, each operation is reversed, so that the logic of output terminal 4 becomes ''1''. in any status, any one of transistors, transistor 7 or transistors in inverters 5 and 6, is connected, so that the impedance in the output terminal 4 is reduced, the rise time and decay time for pulses are shorten and the constant collector current does not flow in the circuits.
JP10783978A 1978-09-02 1978-09-02 Clock driver circuit Pending JPS5534577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10783978A JPS5534577A (en) 1978-09-02 1978-09-02 Clock driver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10783978A JPS5534577A (en) 1978-09-02 1978-09-02 Clock driver circuit

Publications (1)

Publication Number Publication Date
JPS5534577A true JPS5534577A (en) 1980-03-11

Family

ID=14469347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10783978A Pending JPS5534577A (en) 1978-09-02 1978-09-02 Clock driver circuit

Country Status (1)

Country Link
JP (1) JPS5534577A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171280A2 (en) * 1984-08-06 1986-02-12 Advanced Micro Devices, Inc. High-fanout clock driver for low level gates
EP0310232A2 (en) * 1987-09-30 1989-04-05 Kabushiki Kaisha Toshiba Complementary signal output circuit
JP4767465B2 (en) * 1999-10-15 2011-09-07 ボルボ ラストバグナー アーベー Brake disc for vehicle disc brake

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171280A2 (en) * 1984-08-06 1986-02-12 Advanced Micro Devices, Inc. High-fanout clock driver for low level gates
EP0310232A2 (en) * 1987-09-30 1989-04-05 Kabushiki Kaisha Toshiba Complementary signal output circuit
JP4767465B2 (en) * 1999-10-15 2011-09-07 ボルボ ラストバグナー アーベー Brake disc for vehicle disc brake

Similar Documents

Publication Publication Date Title
JPS5696532A (en) Frequency divider
JPS5534577A (en) Clock driver circuit
GB1451732A (en) Signal shaping circuit
JPS5261945A (en) Transistor circuit
JPS5528632A (en) Crystal oscillator circuit unit
JPS57196627A (en) Electronic circuit device
JPS5634233A (en) Complementary level converting circuit
JPS54104272A (en) Complementary mos logic circuit
JPS5648721A (en) Integrated circuit
JPS5493343A (en) Semiconductor integrated circuit
JPS5696530A (en) Driving circuit of tri-state type
JPS5691536A (en) Multiple-valued level output circuit
JPS56117388A (en) Address buffer circuit
KR890004465B1 (en) Delay circuit for gate array
JPS57203334A (en) Semiconductor integrated circuit device
JPS6423617A (en) Fet capacitance driver logic circuit
JPS6423498A (en) Eeprom
JPS5683124A (en) Flip-flop circuit
JPS56111181A (en) Amplifier circuit for logic signal
JPS57122562A (en) Semiconductor integrated circuit
FR2352449A1 (en) Integrated complementary MOS transistor logic circuit - has four pairs of MOS transistors connected to provide three stable states of circuit
JPS5486242A (en) Nor type decoder circuit
JPS567527A (en) High speed frequency division circuit
JPS5516540A (en) Pulse detection circuit
JPS57180224A (en) Flip-flop circuit