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JPS54161270A - Lead frame for integrated-circuit device - Google Patents

Lead frame for integrated-circuit device

Info

Publication number
JPS54161270A
JPS54161270A JP7007878A JP7007878A JPS54161270A JP S54161270 A JPS54161270 A JP S54161270A JP 7007878 A JP7007878 A JP 7007878A JP 7007878 A JP7007878 A JP 7007878A JP S54161270 A JPS54161270 A JP S54161270A
Authority
JP
Japan
Prior art keywords
base ribbon
substrates
lead frame
ribbon
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7007878A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6227544B2 (it
Inventor
Yoshihiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7007878A priority Critical patent/JPS54161270A/ja
Publication of JPS54161270A publication Critical patent/JPS54161270A/ja
Publication of JPS6227544B2 publication Critical patent/JPS6227544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP7007878A 1978-06-09 1978-06-09 Lead frame for integrated-circuit device Granted JPS54161270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7007878A JPS54161270A (en) 1978-06-09 1978-06-09 Lead frame for integrated-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7007878A JPS54161270A (en) 1978-06-09 1978-06-09 Lead frame for integrated-circuit device

Publications (2)

Publication Number Publication Date
JPS54161270A true JPS54161270A (en) 1979-12-20
JPS6227544B2 JPS6227544B2 (it) 1987-06-15

Family

ID=13421138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7007878A Granted JPS54161270A (en) 1978-06-09 1978-06-09 Lead frame for integrated-circuit device

Country Status (1)

Country Link
JP (1) JPS54161270A (it)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178544A (ja) * 1982-04-12 1983-10-19 Matsushita Electronics Corp リ−ドフレ−ム
JPS58209146A (ja) * 1982-05-31 1983-12-06 Nec Corp 半導体装置
JPS60141125U (ja) * 1984-02-27 1985-09-18 エルメック株式会社 電子部品装置
JPS63311748A (ja) * 1987-06-12 1988-12-20 Matsushita Electronics Corp 樹脂封止型マルチチップパッケ−ジ
JPH02148758A (ja) * 1988-11-29 1990-06-07 Matsushita Electron Corp 半導体装置用リードフレーム
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
JPH04364066A (ja) * 1991-06-11 1992-12-16 Mitsui High Tec Inc リードフレームおよびこれを用いた半導体装置
JP2002223828A (ja) * 2001-02-05 2002-08-13 Eiji Hiraiwa 折り畳み傘

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989157A (it) * 1972-12-29 1974-08-26
JPS5174758U (it) * 1974-12-06 1976-06-11
JPS5245056A (en) * 1976-09-27 1977-04-08 Gen Corp Integrated circuit and method of producing same
JPS534868U (it) * 1976-06-29 1978-01-17
JPS538572U (it) * 1976-07-07 1978-01-25

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS534868B2 (it) * 1974-11-22 1978-02-21
JPS51126250A (en) * 1975-04-24 1976-11-04 Sarayama Tetsukoushiyo Kk Method of injection molding gear*pulley or the like

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4989157A (it) * 1972-12-29 1974-08-26
JPS5174758U (it) * 1974-12-06 1976-06-11
JPS534868U (it) * 1976-06-29 1978-01-17
JPS538572U (it) * 1976-07-07 1978-01-25
JPS5245056A (en) * 1976-09-27 1977-04-08 Gen Corp Integrated circuit and method of producing same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178544A (ja) * 1982-04-12 1983-10-19 Matsushita Electronics Corp リ−ドフレ−ム
JPH0517709B2 (it) * 1982-04-12 1993-03-09 Matsushita Electronics Corp
JPS58209146A (ja) * 1982-05-31 1983-12-06 Nec Corp 半導体装置
JPS6250059B2 (it) * 1982-05-31 1987-10-22 Nippon Electric Co
JPS60141125U (ja) * 1984-02-27 1985-09-18 エルメック株式会社 電子部品装置
JPS63311748A (ja) * 1987-06-12 1988-12-20 Matsushita Electronics Corp 樹脂封止型マルチチップパッケ−ジ
JPH02148758A (ja) * 1988-11-29 1990-06-07 Matsushita Electron Corp 半導体装置用リードフレーム
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
JPH04364066A (ja) * 1991-06-11 1992-12-16 Mitsui High Tec Inc リードフレームおよびこれを用いた半導体装置
JP2002223828A (ja) * 2001-02-05 2002-08-13 Eiji Hiraiwa 折り畳み傘

Also Published As

Publication number Publication date
JPS6227544B2 (it) 1987-06-15

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