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JPS54115081A - Manufacture for semiconcuctor integrated circuit device - Google Patents

Manufacture for semiconcuctor integrated circuit device

Info

Publication number
JPS54115081A
JPS54115081A JP2325778A JP2325778A JPS54115081A JP S54115081 A JPS54115081 A JP S54115081A JP 2325778 A JP2325778 A JP 2325778A JP 2325778 A JP2325778 A JP 2325778A JP S54115081 A JPS54115081 A JP S54115081A
Authority
JP
Japan
Prior art keywords
film
silicon
silicon film
mask
taking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2325778A
Other languages
Japanese (ja)
Inventor
Masashi Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2325778A priority Critical patent/JPS54115081A/en
Publication of JPS54115081A publication Critical patent/JPS54115081A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To increase the degree of integration, by reducing the deficiency in channel disconnection through the formation of the protective film by taking the nitride film as a mask, after forming the nitride film on the polycrystal silicon film being the gate electrode.
CONSTITUTION: The silicon oxide film 2 is formed on the major plane 1a of the silicon substrate 1, and the polycrystal silicon film 3 is formed on it. The photo resist 5 is coated on the silicon film 3 and after removing it selectively, the gate electrode 6 is formed. The higg melting point metal film 7 is coated on the silicon film 2 by taking the photo resist 5 as a mask. The photo resist 5 and the metal film 7 are removed with etching, and the silicon nitride film 9 is formed via the silicon oxide film 8 by taking the metal film 7 on the silicon film 2 as a mask. The metal film 7, silicon film 8, and silicon film 9 are removed by etching, forming the protective film on the silicon film 2 on the drain region and the source regions 10,11 and the silicon film of the surface of the electrode 6.
COPYRIGHT: (C)1979,JPO&Japio
JP2325778A 1978-02-28 1978-02-28 Manufacture for semiconcuctor integrated circuit device Pending JPS54115081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2325778A JPS54115081A (en) 1978-02-28 1978-02-28 Manufacture for semiconcuctor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2325778A JPS54115081A (en) 1978-02-28 1978-02-28 Manufacture for semiconcuctor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS54115081A true JPS54115081A (en) 1979-09-07

Family

ID=12105540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2325778A Pending JPS54115081A (en) 1978-02-28 1978-02-28 Manufacture for semiconcuctor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS54115081A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514891A (en) * 1995-06-02 1996-05-07 Motorola N-type HIGFET and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514891A (en) * 1995-06-02 1996-05-07 Motorola N-type HIGFET and method

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