JPH11274155A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved in flexibility and mounting density of wiring design by enabling wiring, even in a low- elastic-modulus layer at corners of the semiconductor chip. SOLUTION: This semiconductor device includes a low elastic modules layer 20, having bevel parts 21A beveled linearly at corners as viewed from a plane and also having a slanted outer edge, pads 30 connected to electrodes of a semiconductor chip 10, a wiring pattern 31 extended perpendicular to an outer edge of the layer 20 from the pads 30 along on the layer 20, lands 32 provided on the layer 20 as being connected to the wiring pattern 31, a solder resist 40 formed so as to cover the pattern other than the lands 32, and metal balls 50 provided on the lands 32. Thereby the wiring pattern 31 is formed with predetermined width and interval at the bevel parts 21A, and thus a semiconductor device can be realized, which is improved in flexibility and mounting density of wiring design.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element such as a transistor, and more particularly to a semiconductor device capable of high-density mounting.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, semiconductor devices have been required to be smaller, denser and faster. For this reason, for example, LOC (lead-on-chip) or SON (small outline non-lead) is used as a memory package.
ΜBG using TAB tape
A (Micro ball grid array)
No. 6-504408).

Hereinafter, a conventional semiconductor device called μBGA will be described with reference to FIG. FIG. 4 (a)
Is a perspective view of a conventional semiconductor device called μBGA, FIG.
FIG. 4B is a cross-sectional view taken along the line IV-IV showing a state before the metal ball is formed in FIG. FIG.
1A and 1B, reference numeral 101 denotes a semiconductor chip having a built-in semiconductor element such as a transistor, 102 denotes a wiring circuit sheet provided on the semiconductor chip 101, and 103 denotes a portion between the semiconductor chip 101 and the wiring circuit sheet 102. An intervening flexible low elastic modulus material film, 104 is a partial lead of the wiring circuit sheet 102, 105 is a semiconductor chip 10
Reference numeral 1 denotes an electrode, 106 denotes a land of the printed circuit sheet 102, and 107 denotes a metal ball provided on the land 106 for connecting the semiconductor device to the outside.

As shown in FIGS. 4A and 4B, μBG
A semiconductor device called A has a structure in which a wiring circuit sheet 102 is bonded to a semiconductor chip 101 via a low elastic modulus material film 103, and an electrode 105 of the semiconductor chip 101.
And a land 106 of the wiring circuit sheet 102 are electrically connected via a partial lead 104, and a metal ball 107 is provided on the land 106.

[0005]

However, according to the above-described conventional semiconductor device, there is a restriction on the partial lead 104 in order to reduce the size. A non-wiring area in which the lead 104 cannot be wired has occurred.

Hereinafter, the non-wiring area will be described with reference to FIG. FIG. 5 is a plan view showing the vicinity of a corner of a conventional semiconductor device. In FIG. 5, in order to reduce the size of the semiconductor device, the partial lead 104 has a minimum length required for bending and connection at a portion extending from the outer edge of the printed circuit sheet 102 and is orthogonal to the outer edge. It is formed so that. Therefore, the wiring circuit sheet 102
In the corner of the semiconductor chip 101, that is, in the vicinity of the corner of the semiconductor chip 101, the interval between the partial leads 104 becomes narrow, so that a non-wiring area 108 where wiring cannot be performed occurs.
Since the partial leads 104 are not provided in the non-wiring area 108, the degree of freedom in wiring design is reduced, and high-density mounting is hindered.

SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device which can be wired even near a corner of a semiconductor chip, thereby improving the degree of freedom in wiring design and achieving high-density mounting. The purpose is to provide.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
As described in claim 1, a semiconductor chip having an electrode on the main surface, an insulating layer provided on the main surface and having an opening on the electrode, and an outer edge of the insulating layer connected to the electrode, A metal wiring provided so as to extend transversely over the insulating layer, and a chamfered portion in which each corner is chamfered in a plan view is provided in a corner of the insulating layer in a plan view. The metal wiring extends at the chamfered portion so as to cross the outer edge of the chamfered portion.

Thus, the metal wiring is provided so as to cross the outer edge at the chamfered portion of the insulating layer when viewed in a plan view, so that it is possible to wire the electrode provided at the corner of the semiconductor chip. And the mounting density are improved. Furthermore, since the distance between the metal wiring provided in the chamfered portion and the center of the semiconductor device is shortened, the thermal stress when a heat cycle is applied is reduced, and thus the peeling of the metal wiring from the insulating layer is suppressed. Is done.

[0010] As described in claim 2 or 3,
In the semiconductor device according to the first aspect, it is preferable that the chamfered portion is chamfered such that an outer edge of each corner portion draws a straight line or an arc when viewed in plan.

Thus, in the chamfered portion, the metal wiring is provided so as to surely cross the outer edge formed so as to draw a straight line or an arc in a plan view, so that the electrode provided at the corner of the semiconductor chip is provided. , The metal wiring is securely wired.

According to a fourth aspect of the present invention, in the semiconductor device of the second or third aspect, an external terminal is provided on the insulating layer so that a portion of the metal wiring extends, and the external terminal is provided with an opening. And a protective film made of an insulating substance having a property of repelling the conductive material.

Thus, when connecting the external terminal of the semiconductor device to the terminal of the external device using the conductive material, the metal wiring other than the external terminal and the electrode of the semiconductor chip are reliably protected from the conductive material. be able to.

According to a fifth aspect of the present invention, in the semiconductor device of the fourth aspect, it is possible to further include a protruding electrode provided on the external terminal.

Thus, the external terminals of the semiconductor device and the terminals of the external equipment can be reliably connected via the protruding electrodes.

According to a sixth aspect of the present invention, in the semiconductor device of the first aspect, it is preferable that the insulating layer has an inclined cross-sectional shape at the opening.

Thus, the metal wiring is stably formed by being provided on the slope at the outer edge of the insulating layer having an inclined cross-sectional shape.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a perspective view schematically showing a semiconductor device according to the present invention, with a part of a solder resist being opened. In FIG. 1, reference numeral 10 denotes a semiconductor chip containing a semiconductor element such as a transistor;
Is an insulating layer provided on the semiconductor chip 10 and has a low elastic modulus layer having a slope at an outer edge portion.
A chamfered portion linearly chamfered at each corner portion of the semiconductor chip 10; 30 a pad provided on an electrode (not shown) of the semiconductor chip 10; A wiring pattern orthogonal to the inside of the semiconductor device, 32 is a land provided on the low elasticity layer 20 and connected to the pad 30 via the wiring pattern 31, and 40 is a solder resist formed so as to cover a portion other than the land 32 Reference numerals 50 denote metal balls provided on the lands 32 for connecting the semiconductor device to the outside. The pad 30, the wiring pattern 31, and the land 32 together form a metal wiring 33.

Here, a feature of the semiconductor device according to the present invention is that each corner of the low elastic modulus layer 20 as viewed in plan has a chamfered portion 21A which is chamfered linearly as viewed in plan. The wiring pattern 31 that passes through the chamfered portion 21A is orthogonal to the outer edge of each chamfered portion 21A of the low elastic modulus layer 20.

Details of the vicinity of each corner in the semiconductor device according to the present invention will be described with reference to FIG. FIG. 2 (a)
FIG. 2B is a plan view showing details in the vicinity of corners of the semiconductor device shown in FIG. 1 and FIG. 2B is a modification of the semiconductor device shown in FIG.

As shown in FIG. 2A, wiring patterns 31 are formed at predetermined intervals perpendicular to the outer edges of the chamfered portions 21A of the low elastic modulus layer 20. As a result, the area of the chamfered portion 21A can be used near each corner, and the degree of freedom in wiring design is improved.

In addition, a land (FIG. 1) on the low elastic modulus layer 20 extends from the electrode 11 provided near each corner of the semiconductor chip 10.
By providing the wiring pattern 31 on the land 32), the number of lands can be increased, so that the mounting density is improved.

A modification of the semiconductor device according to the present invention will be described with reference to FIG. As shown in FIG. 2B, a chamfered portion 21B that is chamfered in an arc shape as viewed in plan can be provided at each corner of the low elastic modulus layer 20 as viewed in plan. Also in this case, the wiring pattern 31 that passes through the chamfered portion 21B is substantially perpendicular to the outer edge of each chamfered portion 21B of the low elastic modulus layer 20. Therefore, each chamfered part 21 having no corners
1B, the degree of freedom in wiring design is further improved, and the lands on the low elastic modulus layer 20 (the lands 32 in FIG. By providing the wiring pattern 31), the number of lands can be increased, so that the mounting density is improved.

As shown in FIG. 2A, the low elastic modulus layer 2
In each of the corners 0, the outer edge is chamfered linearly, and in the conventional case where each corner is a right angle as shown in FIG. The width and the wiring interval were compared. In the case of the conventional semiconductor device shown in FIG.
A wiring rule with a wiring width of 20 μm and a wiring interval of 40 μm was required. On the other hand, in the case of the semiconductor device according to the present invention shown in FIG. 2A, wiring can be performed at each corner according to a wiring rule of a wiring width of 40 μm and a wiring interval of 40 μm.

As described above, according to the present invention, when the same wiring width is used, the degree of freedom in wiring design is improved and the number of wiring patterns is reduced as compared with the conventional semiconductor device. As a result, a semiconductor device with an increased mounting density is realized.

Further, when the number of wiring patterns is the same, the wiring width can be widened, so that a highly reliable semiconductor device is realized.

Further, in each of the semiconductor devices shown in FIGS. 2A and 2B, the wiring pattern 31 and the center of the semiconductor device at the farthest part from the center, that is, at each corner of the low elasticity layer 20. Distance is shortened. This allows
When a thermal cycle is applied, the low modulus layer 20
Stress caused by the difference between the thermal expansion coefficients of the semiconductor device and the wiring pattern 31 is reduced. Therefore, the peeling of the wiring pattern 31 from the low elastic modulus layer 20 is suppressed, and a semiconductor element having high reliability with respect to application of a heat cycle is realized.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG.
(E) is sectional drawing which shows the manufacturing process of the semiconductor device shown in FIG. 1, respectively.

First, as shown in FIG. 3A, an insulating material having photosensitivity and a low elastic modulus is formed on the electrode 11 and the passivation film 12 formed on the main surface of the semiconductor chip 10. After applying the resin, it is dried to form a resin film 15. The photosensitive material for forming the resin film 15 may be a polymer having a low elastic modulus and an insulating property, such as polyimide or epoxy.

Next, as shown in FIG.
Exposure and development are sequentially performed on 5 to form a low elastic modulus layer 20 in which the electrode 11 is opened. In this case,
The low elastic modulus layer 20 is formed such that each corner is chamfered in a straight line or an arc shape in a plan view in the low elastic modulus layer 20. Further, for example, the cross-sectional shape of the low elastic modulus layer 20 in the opening is formed not in a direction perpendicular to the electrode 11 but in a tapered shape by using scattered light instead of parallel light in the exposure.

Next, as shown in FIG. 3C, a metal thin film layer made of, for example, Ti / Cu is formed on the entire main surface of the semiconductor chip 10 by vacuum evaporation, sputtering, CVD or electroless plating. Is formed, the metal thin film layer is patterned. As a result, on the main surface of the semiconductor chip 10, the predetermined metal wiring 3 including the pad 30, the wiring pattern 31, and the land 32 is formed.
Form 3 The pattern of the metal wiring 33 is
, That is, the number of pins and the area of the semiconductor chip 10 are determined.

The patterning is performed as follows.
A photosensitive resist is applied on the metal thin film layer, and the resist other than a predetermined pattern portion is cured by exposure, and then the resist in the pattern portion is removed. A metal layer having a large thickness, for example, made of Cu is formed on the pattern portion by using electrolytic plating, and then the resist is melted and removed. Thereafter, a predetermined metal wiring is formed by immersing the metal thin film layer in an etchant and leaving the metal layer having a large thickness.

A metal film is deposited on the entire surface, a photoresist is applied thereon, and a resist for an etching mask is formed on a predetermined pattern portion using a photolithography technique. The metal wiring may be formed by etching the metal layer.

Next, as shown in FIG. 3D, after applying a photosensitive solder resist on the low elastic modulus layer 20,
Using a photolithography technique, the solder resist 40 is formed so that only the land 32 is exposed. The solder resist 40 protects the pad 30 and the wiring pattern 31, which are portions of the metal wiring other than the land 32, from solder melted in a later step.

Next, as shown in FIG.
A metal ball 50 made of copper, nickel, or the like, or made of solder-plated metal is placed on the land 32,
The metal ball 50 and the land 32 are melt-bonded. Through the above steps, a semiconductor device according to the present invention can be obtained.

According to the method of manufacturing a semiconductor device of the present embodiment, the low elastic modulus layer 20 is formed such that each corner is straightly or arcuately chamfered in plan view. Therefore, the semiconductor device according to the present invention can be easily manufactured.

In the above description, the cross-sectional shape of the low elastic modulus layer 20 at the opening is tapered.
Instead, the shape may be an arc shape, and the cross section may be perpendicular to the main surface of the semiconductor chip.

The low elastic modulus layer 20 is exposed and developed by exposure.
However, instead of this, the low elastic modulus layer 20 in which each corner is chamfered linearly or arcuately in plan view may be formed by using, for example, a screen printing method.

Further, in order to form the resin film 15, a resin made of an insulator having photosensitivity and low elastic modulus was applied. However, the present invention is not limited thereto, and a photosensitive insulating material formed in a film shape in advance may be used. In this case, the semiconductor chip 10 is exposed and developed after a film-like insulating material is bonded onto the semiconductor chip 10.
Is exposed.

Further, an insulating material having no photosensitivity can be used. In this case, the electrodes 11 of the semiconductor chip 10 are exposed by mechanical processing such as laser or plasma, or chemical processing such as etching.

[0041]

According to the present invention, since the metal wiring is provided so as to cross the outer edge of the chamfered portion of the insulating layer in plan view, the metal wiring is also provided for the electrode provided at the corner of the semiconductor chip. As a result, a semiconductor device with improved wiring flexibility and packaging density is realized.

Further, since the distance between the metal wiring provided in the chamfered portion and the center of the semiconductor device is reduced, the thermal stress when a thermal cycle is applied is reduced. Therefore, the peeling of the metal wiring from the insulating layer is suppressed,
A semiconductor device having high reliability against a thermal cycle is realized.

Further, since the metal wiring is provided on the slope at the outer edge of the insulating layer having an inclined cross-sectional shape, it is formed stably.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a semiconductor device according to the present invention with a part of a solder resist being opened.

FIG. 2A is a view of the semiconductor device shown in FIG.
FIG. 3 is a plan view showing details of the vicinity of each corner of a modification of the semiconductor device shown in FIG. 1.

FIGS. 3A to 3E are cross-sectional views each showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 4A is a perspective view of a conventional semiconductor device called μBGA, and FIG. 4B is a cross-sectional view taken along line IV-IV showing a state before a metal ball is formed in FIG.

5 is a plan view showing the vicinity of a corner of the conventional semiconductor device shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 semiconductor chip 11 electrode 12 passivation film 15 resin film 20 low elasticity layer (insulating layer) 21A, 21B chamfered portion 30 pad 31 wiring pattern 32 land (external terminal) 33 metal wiring 40 solder resist (protective film) 50 metal ball ( Protruding electrode)

Continuation of the front page (72) Inventor Takahiro Kumakawa 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (6)

[Claims] A semiconductor chip having an electrode on a main surface, an insulating layer provided on the main surface and having an opening on the electrode, connected to the electrode, and traversing an outer edge of the insulating layer; A metal wiring provided so as to extend in the lateral direction on the insulating layer, and a chamfered portion in which each corner is chamfered in a plan view is provided in a corner of the insulating layer in a plan view. Wherein the metal wiring extends in the chamfered portion so as to cross an outer edge of the chamfered portion. 2. The semiconductor device according to claim 1, wherein the chamfered portion is chamfered such that an outer edge of each of the corners draws a straight line in a plan view. 3. The semiconductor device according to claim 1, wherein the chamfered portion is chamfered such that an outer edge of each of the corners draws an arc in a plan view. 4. The semiconductor device according to claim 2, wherein a part of the metal wiring extends on the insulating layer, and a conductive material provided on the opening of the external terminal is provided. A semiconductor device further comprising a protective film made of an insulating material having a repelling property. 5. The semiconductor device according to claim 4, further comprising a protruding electrode provided on said external terminal. 6. The semiconductor device according to claim 1, wherein the insulating layer has a cross section that is inclined at the opening.