JP3313058B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device incorporating a semiconductor element such as a transistor and a method of manufacturing the same, and more particularly to a measure for improving the reliability of a wiring portion.

[0002]

2. Description of the Related Art In recent years, a semiconductor device and a method for manufacturing the same have been required to have a smaller size, a higher density, and a higher speed as electronic devices have become smaller and more sophisticated. Development of LOC (lead-on-chip) or SON (small outline non-lead), or μB using TAB tape
Packages such as GA (Micro Ball Grid Array) (Japanese Patent Application Laid-Open No. 06-504408) have been developed.

Hereinafter, a conventional semiconductor device called μBGA and a method of manufacturing the same will be described with reference to the drawings.

FIG. 10 is a sectional view showing a conventional semiconductor device called μBGA. In FIG. 10, 101 is a semiconductor chip having a built-in semiconductor element, 102 is a wiring circuit sheet formed on the semiconductor chip 101, and 103 is a flexible low elastic modulus material interposed between the semiconductor chip 101 and the wiring circuit sheet 102. , 104 are partial leads that become a part of a wiring layer, 105 is a chip contact electrically connected to a semiconductor element in the semiconductor chip 101, and 106 is formed on the surface of the wiring circuit sheet 102 and is electrically connected to an external device. This is an electrode for making connection.

As shown in FIG. 1, a conventional semiconductor device called μBGA has a structure in which a wiring circuit sheet 102 is formed on a semiconductor chip 101 with a low elastic modulus material 103 interposed therebetween. Top chip contact 1
05 and the electrode 106 on the surface of the printed circuit sheet 102 are electrically connected by partial leads 104.

That is, by adopting such a structure of the semiconductor device, it becomes possible to electrically connect to an external device through a large number of electrodes 106 two-dimensionally formed on the printed circuit sheet 102. Therefore, it is intended to reduce the size of information communication equipment, office electronic equipment, and the like.

[0007]

However, in the above-mentioned conventional semiconductor device, when the semiconductor device is subjected to a thermal cycle test in which heating and cooling are repeated, the partial lead 104 may be broken. That is, there is a problem that the reliability of the wiring formed on the surface of the semiconductor device is not always guaranteed.

The present inventors have investigated the cause, and as a result, have found that the entire base between the chip contact 105 on the semiconductor chip 101 and the electrode 106 on the surface of the wiring circuit sheet 102 and the metal forming the wiring layer It is presumed that the thermal stress, especially the tensile stress, generated due to the difference in the thermal expansion coefficient (thermal shrinkage) from the film cannot be sufficiently absorbed by the elasticity of the wiring layer.

The present invention has been made in view of such a point, and an object of the present invention is to heat and heat a semiconductor device as described above.
It is an object of the present invention to provide a semiconductor device having a highly reliable wiring layer and a method of manufacturing the same by taking measures for absorbing thermal stress applied to the wiring layer by cooling.

[0010]

To achieve the above object, according to the solution to ## measure taken by the present invention is Ru near providing the meandering part for absorbing the stress of thermal stress or the like to the metal wiring.

A first semiconductor device according to the present invention comprises: a semiconductor chip having electrodes disposed on a surface thereof ;
And an opening is formed in a region where the electrodes are arranged.
A semiconductor having an end portion of the opening,
Insulation with wedge-shaped ramps to the surface of the chip
A material layer and a meandering portion extending from the electrode on the semiconductor chip and meandering at least once , straddling the low elastic modulus layer;
And a metal wiring formed by the method.

Thus, even when a stress such as thermal stress, particularly a tensile stress is applied to the semiconductor device due to heating / cooling of the semiconductor device, the stress is absorbed in the meandering portion of the metal wiring. Can be prevented, and the reliability is improved. In addition, the metal wiring can be provided along the inclined portion of the low elastic modulus layer, and the reliability against disconnection is further improved.

According to a second semiconductor device of the present invention, there is provided a semiconductor chip having electrodes disposed on a surface thereof ,
And an opening is formed in a region where the electrodes are arranged.
Has, electrodes on the semiconductor chip from the edge of the opening
Having at least one protrusion in the region leading to
A metal layer having a meandering portion extending from the upper surface of the insulating material layer to the electrode on the semiconductor chip via the convex portion, and meandering vertically along the surface of the convex portion. I have.

[0014] This also ensures that the metal wiring has a meandering portion.

The insulating material layer is a low elastic modulus layer.
In addition, the low elasticity layer can reduce the impact force applied to the metal wiring and the like, and can absorb the stress such as the thermal stress generated due to the difference in the thermal expansion coefficient between the low elasticity layer and the metal wiring, further improving reliability. improves.

The above-mentioned metal is formed on the above-mentioned insulating material layer.
Further having external electrode terminals connected to the wiring
The first method of manufacturing a semiconductor device of the present invention is preferably
On a semiconductor chip having an electrode, an insulating material containing an organic solvent component to form the insulating material film, by drying the insulating material film, insulation <br/> edge material that have a concavo-convex pattern on the surface a first step of forming a film, and patterning the insulating material layer, a second step that form openings over the regions of the electrode, the region including the top of at least said insulating material layer Forming a metal wiring connected to the electrode of the semiconductor chip.

According to this method , the metal wiring formed on the insulating material film has a meandering shape in the vertical direction on the uneven pattern, so that it has a high function of absorbing stress such as thermal stress and preventing disconnection. A metal wiring is formed. Therefore, a highly reliable semiconductor device is formed. In particular, this one
By the method , an uneven pattern can be formed very easily on the surface of the insulating material film .

According to a second method of manufacturing a semiconductor device of the present invention,
On a semiconductor chip having an electrode, a first step of forming an insulating material layer, and patterning the insulating material film,
A second step that form an opening above the electrode, the
A third step of patterning an upper surface of the insulating material film to form a concavo-convex pattern, and a fourth step of forming a metal wiring connected to an electrode of the semiconductor chip in a region including at least the upper part of the insulating material film. It has.

[0019] Also by this method, since the uneven pattern is formed on the surface of the insulating material layer, it is possible to meander the metallic wiring in the vertical direction, no disconnection even when stress such as thermal stress is applied A highly reliable semiconductor device is formed.

The insulating material film is a low elastic modulus layer
Is preferred.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view showing the semiconductor device according to the first embodiment with a part of a solder resist being opened. FIGS. 2 and 3 show a portion between an end portion of a low elastic modulus layer and an electrode on a semiconductor chip. FIG. 4 is a partial perspective view showing an enlarged portion of FIG.

In FIG. 1, reference numeral 10 denotes a semiconductor chip having therein a semiconductor integrated circuit constituted by semiconductor elements such as transistors. A pad 30 connected to an electrode (not shown) of the semiconductor chip 10 is arranged at the center of the main surface of the semiconductor chip 10. Further, on the main surface of the semiconductor chip 10, a low elastic modulus layer 20 made of an insulating material having a low elastic modulus is provided in a region other than the central portion where the pads 30 are arranged. This low modulus layer 20
Has a wedge-shaped inclined portion reaching the main surface of the semiconductor chip 10 on which the pad 30 is formed. Low modulus layer 2
A land 32 functioning as an external electrode terminal for inputting / outputting a signal between a semiconductor element in the semiconductor chip 10 and an external device is provided on the semiconductor chip 10.
A metal wiring 31 is provided for connecting between the pad and the pad 30. The pad 30, the metal wiring 31, and the land 32 are made of the same metal layer, and together form a metal wiring pattern. On the land 32, a metal ball 40, which is a protruding electrode, is provided. On the entire semiconductor device, a solder resist 5 exposing a region where the metal ball 40 is formed and covering the other region is formed.
0 is formed. That is, the metal ball 40 is bonded to the land 32 exposed at the opening of the solder resist 50.

The area other than the pads 30 on the main surface of the semiconductor chip 10 is covered with a passivation film (not shown).

Here, a feature of the semiconductor device according to this embodiment is that at least a part of the metal wiring 31 is configured to meander. In other words, a meandering portion is formed in the metal wiring 31 once or twice or more. That is, the meandering portion is configured to absorb a stress such as a thermal stress generated due to heating and cooling of the semiconductor device.

However, the meandering portion of the metal wiring 31 may have a shape in which the entire metal wiring 31 is meandering as shown in FIG. 2, or the lower elastic modulus layer 20 of the metal wiring 31 as shown in FIG. The shape may meander only on the inclined portion.

According to the semiconductor device of this embodiment, the land 3 serving as an external electrode terminal is two-dimensionally provided on the main surface of the semiconductor device.
2 are arranged, so that a large number of external electrode terminals can be provided in a small area, and the pads 30 and the lands 32 can be connected by the patternable metal wiring 31. Therefore, the semiconductor device is a small and thin semiconductor device and can cope with an increase in the number of pins.

In particular, since the meandering metal wiring 30 is provided on the low elastic modulus layer 20 serving as a base, when the semiconductor device is mounted on a mother board such as a printed board, etc.
Even if a stress such as a thermal stress is applied to the metal wiring 30 due to heating and cooling of the semiconductor device, the metal wiring 30 meanders, so that the tensile stress applied to the metal wiring 30 is reduced. Therefore, disconnection of the metal wiring 30 at the time of mounting on a substrate or the like can be prevented, and a highly reliable wiring structure can be realized.

A land 32 connected to the metal wiring 30
Since the metal ball 40 serving as an external electrode is provided on the substrate, the process of mounting the semiconductor device on a mother substrate such as a printed circuit board can be performed extremely easily and quickly. The thermal stress generated from the metal ball 40 can be absorbed.

Next, the results of a reliability test performed on the wiring structure of this embodiment will be described.

A semiconductor device having basically the same structure as the semiconductor device of the present embodiment, but having all the metal wirings in a straight line,
Mount on glass epoxy board (FR-4) with solder (63Sn / 37Pb), -55 ° C (30 minutes)-150 ° C
As a result of performing a heat cycle test (30 minutes), the reliability when the metal wiring layer was not meandered was 600 cycles, and the cause of the open failure was a disconnection at the end face of the metal wiring.

On the other hand, as shown in FIG. 2, the semiconductor device of this embodiment having a metal wiring in which all portions meander is used.
As a result of mounting under the same conditions as above and performing a thermal cycle test under the same conditions as above, the reliability was improved to 1500 cycles. However, the width of the metal wiring is fixed at 50
μm, the meandering shape has one amplitude for a length of 200 μm, and the amplitude is 75 μm.

The same thermal cycle test as described above was conducted on the metal wiring which is meandering only on the inclined portion and straight in the other portion of the low elastic modulus layer 20 as shown in FIG. As a result, the reliability was improved up to 1200 cycles.

By making the meandering pattern of each metal wiring 31 the same, the patterning property on the low elasticity layer 20 when forming the metal wiring 31 is improved, and the contact between the metal wirings 31, that is, Short circuit can be prevented.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. FIG. 4 is a perspective view showing the solder resist of the semiconductor device of the second embodiment with a full opening, and FIG. 5 shows a portion between the end of the low elastic modulus layer and the electrode on the semiconductor chip. It is a partial perspective view which expands and shows.

As shown in FIG. 4, in the semiconductor device according to the present embodiment, pads 30 connected to electrodes (not shown) of the semiconductor element are arranged on the outer peripheral portion on the main surface of the semiconductor chip 10. ing. In addition, the semiconductor chip 10
A low elastic modulus layer 20 made of an insulating material having a small elastic modulus is provided on the main surface of the substrate except for the outer peripheral portion where the pad 30 is arranged. Unlike the first embodiment, the low elastic modulus layer 20 does not have an inclined portion and is formed to have a step with respect to the main surface of the semiconductor chip 10. The wiring circuit sheet 35 is provided on the low elastic modulus layer 20. This wiring circuit sheet 35
Has a wiring pattern (not shown) formed by patterning a copper foil on a flexible sheet. And
In the present embodiment, the wiring on the wiring circuit sheet 35 is
A metal lead 31 is constituted by a partial lead derived from this wire and connected to the pad 30. here,
The wiring on the wiring circuit sheet 35 is meandering, and the wiring width on the wiring circuit sheet 35 is narrow. And
As shown in FIG. 5, the partial lead of the metal wiring 31 led out from the wiring circuit sheet 35 meanders at the stepped portion and extends without being in close contact with the base, and extends at the pad 30 serving as an end thereof. It is configured to be connected to the electrode 11 on the semiconductor chip 10 by thermocompression.

The metal wiring 3 on the wiring circuit sheet 35
At one end, a land 32 is provided which functions as an external electrode terminal for inputting / outputting a signal between a semiconductor element in the semiconductor chip 10 and an external device. On the land 32, a metal ball 40, which is a protruding electrode, is provided.

Also in the semiconductor device of the present embodiment, since the metal wiring 31 has a meandering shape, the first
As in the embodiment, the effect of improving the reliability of the wiring layer can be exhibited.

Specifically, a semiconductor device having basically the same structure as the semiconductor device of the present embodiment but having no meandering metal wiring is connected to a glass epoxy substrate by solder (63Sn / 37Pb). -55 ° C (30 minutes)-15
As a result of performing a thermal cycle test at 0 ° C. (30 minutes), the reliability was 400 cycles, and the cause of the open failure was a disconnection at the end face of the metal wiring. However, the width of the metal wiring from the metal wiring inside the wiring circuit sheet to the end, the end face and the pad on the semiconductor chip is a constant 50 μm width.

On the other hand, the semiconductor device having the meandering metal wiring of this embodiment was subjected to a thermal cycle test under the same conditions as described above, and as a result, the reliability was improved to 900 cycles. However, the metal wiring has the same constant width of 50 μm,
The meandering shape has an amplitude of 1 for 200 μm length and an amplitude of 7
It is 5 μm.

(Third Embodiment) Next, a third embodiment will be described with reference to FIG. FIG. 6 is an enlarged partial cross-sectional view showing only the vicinity of the end of the semiconductor device according to the present embodiment.

The structure of the entire semiconductor device according to this embodiment is substantially the same as that of the semiconductor device according to the second embodiment, and the same components as those in the second embodiment have the same reference numerals as those in FIG. The reference numerals are attached and the description is omitted.

As shown in FIG. 6, in the semiconductor device of the present embodiment, two ring-shaped convex low elastic modulus layers 20 surrounding the low elastic modulus layer 20 are formed on the sides of the end of the low elastic modulus layer 20.
a and 20b are further formed. The convex low elastic modulus layers 20a and 20b are formed in a mountain-like cross section.
The metal wiring 31 is formed on the convex low elastic modulus layers 20a and 20b, so that the metal wiring 31 is meandering in the vertical direction. In this embodiment, no printed circuit sheet is provided.

In the semiconductor device of the present embodiment, the reliability was evaluated by the same thermal cycle test as in the second embodiment, and as a result, the reliability was improved to 1600 cycles.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG. FIG. 7 is an enlarged partial cross-sectional view showing only the vicinity of the end of the semiconductor device according to the present embodiment.

The structure of the entire semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and the same components as those in the first embodiment have the same reference numerals as those in FIG. The reference numerals are attached and the description is omitted.

As shown in FIG. 7, in the semiconductor device of the present embodiment, a wavy uneven pattern is provided on the inclined portion of the low elastic modulus layer 20, and the metal wiring 31 has a low elasticity having the uneven pattern. By being formed on the inclined portion of the rate layer 20, it is in a meandering state in the vertical direction.

As described above, by providing an uneven pattern on the inclined portion of the low elastic layer 20, in other words, by gradually reducing the unevenness, the low elastic layer 20 and the pad on the semiconductor chip 10 are formed. The height difference between the electrode 30 and the electrode 30 is reduced, so that the thermal stress between the wirings due to heating and cooling can be further reduced, and the reliability can be improved.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIG. FIG. 8 is an enlarged partial cross-sectional view showing only the vicinity of the center of the semiconductor device according to the present embodiment.

The overall structure of the semiconductor device according to this embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and the same components as those in the first embodiment have the same reference numerals as those in FIG. The reference numerals are attached and the description is omitted.

Here, the feature of the semiconductor device in this embodiment is that a wavy uneven pattern is provided on the entire flat portion of the low elastic modulus layer 20. Then, the metal wiring 31
Among them, a concave and convex pattern is formed in a portion excluding the partial lead, and most of the metal wiring 31 is meandering vertically in the concave and convex pattern.

The reliability of the semiconductor device of this embodiment was evaluated by the same thermal cycle test as in the first embodiment. As a result, the reliability was improved to 1300 cycles.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 9A to 9E are cross-sectional views showing a manufacturing process for realizing the structure of the semiconductor device shown in FIG.

First, as shown in FIG. 9A, the semiconductor chips 10 formed on the main surface
The insulating material film 21 is formed by applying a photosensitive insulating material on the electrode 11 and the passivation film 12 and drying the applied insulating material. As the insulating material, for example, a polymer having a low elastic modulus and an insulating property such as polyimide, epoxy or the like having a low elastic modulus may be used. Here, an epoxy-based material containing 50 wt% of an organic solvent component was applied as an insulating material, and this was dried and used. In this drying step, the organic solvent component in the insulating material film 21 is reduced to 10 wt%, and the volatilization of the organic solvent component forms a ripple-like wrinkle pattern (wavy uneven pattern) on the surface of the insulating material film 21.

Next, as shown in FIG. 9B, the dried insulating material film 21 is sequentially exposed and developed,
A low elastic modulus layer 20 having an opening in the electrode 11 of the semiconductor chip 10 is formed. In this case, for example, the cross-sectional shape of the low elastic modulus layer 20 at the opening is formed not in a direction perpendicular to the main surface of the semiconductor chip 10 but in a tapered shape by using scattered light instead of parallel light in the exposure. At this time, the thickness of the low elastic modulus layer 20 made of an insulating resin was 100 μm.

Next, as shown in FIG. 9C, on the main surface of the semiconductor chip 10, for example, Ti / Ti is deposited by a vacuum deposition method, a sputtering method, a CVD method or an electroless plating method.
After forming the metal thin film layer made of Cu, the metal thin film layer is patterned. As a result, the pad 30 and the metal wiring 3 are formed on the main surface of the semiconductor chip 10.
A predetermined wiring pattern composed of 1 and lands 32 is formed. The wiring pattern is determined in consideration of the number of pads 30, that is, the number of pins and the area of the semiconductor chip 10.

The patterning is performed as follows.
A photosensitive resist is coated on the metal thin film layer, the surface of the low elastic modulus layer 20 is focused and exposed, and the photosensitive resist other than a predetermined pattern portion is cured by the exposure, and then the photosensitive resist is exposed. The resist is removed. In this manner, by exposing the surface of the low elastic modulus layer 20 to focus, it is possible to form fine metal wirings (narrow portions) on the surface of the low elastic modulus layer 20, Layer 2
The metal wiring (wide portion) from the end of the low elastic modulus layer 20 which does not need to be finer as the wiring above 0 to the electrode 11 on the surface of the semiconductor chip 10 can be exposed at the same time, and the number of steps can be reduced.

Thereafter, a metal layer having a large thickness, for example, made of Cu is formed on the pattern portion by using electrolytic plating, and thereafter, the photosensitive resist is melted and removed. Thereafter, a predetermined wiring pattern is formed by immersing the metal thin film layer in an etchant and leaving the metal layer having a large thickness.

A metal film is deposited on the entire surface, a resist is applied thereon, and a resist for an etching mask is formed on a predetermined pattern portion by using a photolithography technique. May be etched to form a wiring pattern.

Next, as shown in FIG. 9D, after applying a photosensitive solder resist on the low elastic modulus layer 20,
The solder resist 50 is formed using a photolithography technique so that only the land 32 is exposed. The solder resist 50 protects the pad 30 and the metal wiring 31 which are portions other than the land 32 in the wiring pattern from the molten solder.

Next, as shown in FIG.
A metal ball 40 made of solder-plated copper, nickel, or the like is placed on the land 32, and the metal ball 40 and the land 32 are melt-bonded. Through the above steps, the semiconductor device according to the present embodiment can be obtained.

In the method of manufacturing a semiconductor device according to the present embodiment,
A step is formed at the end of the opening of the low elastic modulus layer 20 for exposing the electrode 11 on the surface of the semiconductor chip 10, instead of providing a step, and formed so as to be smoothly connected to the surface of the semiconductor chip 10. It is possible to form a structure in which the metal wiring 31 can be easily formed and is hardly broken.

In the description of the present embodiment, a photosensitive insulating material is applied in order to form the low elastic modulus layer 20. However, the present invention is not limited to this. May be used. In this case, after the film-shaped insulating material is bonded onto the semiconductor chip 10 and then exposed and developed, the semiconductor chip 1
It is sufficient that the zero electrode 11 can be exposed.

Further, an insulating material having no photosensitivity can be used. In this case, the electrodes 11 of the semiconductor chip 10 can be exposed by mechanical processing such as laser or plasma or chemical processing such as etching.

Although Ti / Cu is used for the metal thin film layer, Cr, W, Cu, Ni or the like may be used instead.

(Modification of Fifth Embodiment) Next, a modification of the method for manufacturing a semiconductor device of the fifth embodiment will be described. The structure of the semiconductor device of the present embodiment is the same as the structure shown in FIG.

In this embodiment, the process shown in FIG. 9A in the fifth embodiment is basically the same as the process in the fifth embodiment. And the formation of an uneven pattern due to volatilization of the organic solvent component is not performed.

FIG. 9 in the fifth embodiment.
In the step shown in FIG. 5B, the dried insulating material film 21 is sequentially exposed and developed to be patterned, and an uneven pattern is formed on the surface of the insulating material film by an etching method or the like. Thereafter, the low elastic modulus layer 20 is formed and the semiconductor chip 10 is formed.
The electrode 11 is opened and exposed.

However, the formation of the concavo-convex pattern on the surface of the insulating material film by an etching method or the like may be performed after the electrode 11 of the semiconductor chip 10 is opened and exposed.

Also in this modified embodiment, the insulating material having photosensitivity does not need to be in a liquid state, and may be a material formed in a film shape in advance. It suffices if a film-like material is attached to the semiconductor chip, exposed and developed, so that the electrodes of the semiconductor chip can be exposed.

The thickness of the low elastic modulus layer in each of the above embodiments is preferably 10 to 150 μm.

[0072]

According to the semiconductor device of the present invention , a meandering portion is provided in the metal wiring connected to the electrode on the surface of the semiconductor device, so that stress such as thermal stress applied by heating / cooling of the semiconductor device can be reduced. Absorption in the meandering portion can prevent disconnection of the metal wiring, so that a highly reliable semiconductor device can be provided.

According to the method of manufacturing a semiconductor device of the present invention,
As a method of manufacturing a semiconductor device, an insulating material film having a concavo-convex pattern is formed on a semiconductor chip, and a metal wiring is formed thereon, so that a metal wiring meandering in the vertical direction can be easily formed. Thus, a highly reliable semiconductor device having a metal wiring having a high function of preventing disconnection due to application of stress can be formed.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structure of a semiconductor device according to a first embodiment with a solder resist partially opened;

FIG. 2 is a partial perspective view showing, in an enlarged manner, a portion between an end of a low-modulus layer of a semiconductor device having metal wirings meandering in the first embodiment and an electrode of a semiconductor chip; is there.

FIG. 3 is a partial perspective view showing, in an enlarged manner, a portion between an end of a low-modulus layer of a semiconductor device having partially meandering metal wiring and an electrode of a semiconductor chip according to the first embodiment; is there.

FIG. 4 is a perspective view showing a structure of a semiconductor device provided with a printed circuit sheet according to a second embodiment with a solder resist entirely opened;

FIG. 5 is an enlarged partial perspective view showing a region between an end of a low-modulus layer of a semiconductor device and an electrode of a semiconductor chip in a second embodiment.

FIG. 6 is a partial cross-sectional view of a semiconductor device including a convex low-modulus layer according to a third embodiment.

FIG. 7 is a partial cross-sectional view of a semiconductor device provided with a low elastic modulus layer having an inclined portion having a concavo-convex pattern according to a fourth embodiment.

FIG. 8 is a partial cross-sectional view of a semiconductor device provided with a low-modulus layer having an uneven pattern formed on a surface according to a fifth embodiment.

FIG. 9 is a sectional view illustrating a manufacturing step of a semiconductor device according to a fifth embodiment.

FIG. 10 is a cross-sectional view of a conventional semiconductor device including a low elastic modulus layer.

[Explanation of symbols]

 Reference Signs List 10 semiconductor chip 11 electrode 20 low elastic modulus layer 20a, 20b convex low elastic modulus layer 30 pad 31 wiring 32 land 35 wiring circuit sheet 40 metal ball 50 solder resist

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takahiro Kumakawa 1-1, Komachi, Takatsuki City, Osaka Prefecture Inside Matsushita Electronics Corporation (56) References JP-A-9-260535 (JP, A) JP-A Heisei 9-260536 (JP, A) JP-A-9-306945 (JP, A) JP-A-63-72143 (JP, A) JP-A-9-64049 (JP, A) JP-A 9-219463 (JP, A) A) JP-A-11-54649 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/12 H01L 21/60

Claims (8)

(57) [Claims] A semiconductor chip having electrodes disposed on a surface thereof; and a semiconductor chip formed on the semiconductor chip and having the electrodes disposed thereon.
Opening in the area where
And a wedge from the top surface to the surface of the semiconductor chip.
An insulating material layer having an inclined portion, and a metal wiring extending from the electrode on the semiconductor chip, having a meandering portion which is meandered at least once , and formed over the insulating material layer . A semiconductor device characterized by the above-mentioned. 2. A semiconductor chip having electrodes disposed on a surface thereof; and a semiconductor chip formed on the semiconductor chip and having the electrodes disposed thereon.
Having an opening in the region where
At least one protrusion is provided in a region reaching the electrode on the semiconductor chip.
An insulating material layer having a convex portion, and a meandering portion extending from the upper surface of the insulating material layer to the electrode on the semiconductor chip via the convex portion and meandering vertically along the surface of the convex portion. And a metal wiring having the following. 3. The semiconductor device according to claim 1, wherein
Te, the insulating material layer is characterized by a low elastic modulus layer
Semiconductor device. 4. The semiconductor device according to claim 2, wherein Formed on the insulating material layer and connected to the metal wiring
Characterized by further comprising an external electrode terminal
Semiconductor device. 5. The semiconductor device according to claim 2, wherein The insulating material layer is provided at an end of the opening,
Has a wedge-shaped slope from the surface to the surface of the semiconductor chip.
A semiconductor device characterized in that: 6. A on a semiconductor chip having an electrode, an insulating material containing an organic solvent component to form the insulating material film, by drying the insulating material film, insulation that having a concave and convex pattern on the surface a first step of forming a material film, and patterning the insulating material layer, a second step that form openings over the regions of the electrodes, in a region including the top of at least said insulating material layer And a third step of forming a metal wiring connected to the electrode of the semiconductor chip. 7. A on a semiconductor chip having an electrode, a first step of forming an insulating material layer, and patterning the insulating material layer, a second step that form an opening above the electrode A third step of patterning an upper surface of the insulating material film to form a concavo-convex pattern, and a fourth step of forming a metal wiring connected to an electrode of the semiconductor chip at least in a region including above the insulating material film . And a method for manufacturing a semiconductor device. 8. A method for manufacturing a semiconductor device according to claim 6.
In the method, the insulating material film is a low-modulus layer.
A method for manufacturing a semiconductor device.