JP4513973B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to an electronic component and a semiconductor device, a manufacturing method and a mounting method thereof, a circuit board, and an electronic device, and in particular, a small electronic component and a semiconductor device whose package size is close to a chip size, a manufacturing method and a mounting method thereof, a circuit board, and It relates to electronic equipment.

  In pursuit of high-density mounting of semiconductor devices, bare chip mounting is ideal. However, bare chips are difficult to guarantee quality and handle. Therefore, a CSP (chip scale package) having a package close to the chip size has been developed.

  Among the CSP-type semiconductor devices developed in various forms, as one form, a patterned flexible substrate is provided on the active surface side of the semiconductor chip, and a plurality of external electrodes are formed on the flexible substrate. There is something that has been. It is also known to absorb heat stress by injecting resin between the active surface of a semiconductor chip and a flexible substrate. JP-A-7-297236 describes using a film carrier tape as a flexible substrate.

  In these semiconductor device manufacturing methods, a semiconductor chip is cut from a wafer and each semiconductor chip is mounted on a flexible substrate. Therefore, in addition to the need for a patterned flexible substrate and a process for individually mounting a semiconductor chip on the flexible substrate, for example, the apparatus used in each process must also use a dedicated apparatus, which is costly. It was high.

  A semiconductor device to which a CSP type package is applied is a surface mount type, and has a plurality of bumps for mounting on a circuit board. Further, it is preferable to protect the surface on which the bump is formed by providing a photosensitive resin or the like.

  However, since the photosensitive resin is electrically insulative and cannot be mounted if it remains attached on the bump, it is necessary to remove the photosensitive resin from the bump. Here, in order to remove a part of the photosensitive resin, it is necessary to apply lithography, and there is a problem that the number of processes increases.

As described above, the conventional semiconductor device is inefficient in the process from manufacturing to mounting.
JP-A-7-297236 JP-A 64-1257 JP-A-8-203906 JP-A-8-250549 JP-A-52-8785 JP-A-3-198342 Japanese Patent Laid-Open No. 5-291262 JP-A-4-10429 JP-A-6-77283 JP-A-5-226416

  The present invention solves the above-described problems, and an object of the present invention is to provide an electronic component and a semiconductor device capable of efficiently performing processes from manufacturing to mounting, a manufacturing method and mounting method thereof, a circuit board, and To provide electronic equipment.

A method of manufacturing a semiconductor device according to the present invention includes a step of preparing a wafer on which an electrode is formed,
Providing a stress relaxation layer on the wafer so as to avoid at least a portion of the electrode;
Forming a wiring from the electrode to the stress relaxation layer;
Forming an external electrode connected to the wiring above the stress relaxation layer;
Cutting the wafer into individual pieces;
Have

  According to the present invention, the stress relaxation layer is formed on the wafer, and further, the wiring and the external electrode are laminated thereon, so that the semiconductor package can be manufactured in the wafer state. A substrate such as a film provided and patterned in advance is not necessary.

  Here, the stress relaxation layer refers to a layer that relieves stress caused by distortion between the mother board (mounting substrate) and the semiconductor chip. For example, this stress is generated by heat applied when the semiconductor device is mounted on the mounting substrate and thereafter. For the stress relaxation layer, a flexible material or a gel material is selected.

  In addition, since the wiring connecting the electrode and the external electrode can be freely formed according to the design, the arrangement of the external electrode can be determined regardless of the arrangement of the electrodes. Therefore, various semiconductor devices having different positions of the external electrodes can be easily manufactured without changing the circuit design of the elements formed on the wafer.

  Furthermore, according to the present invention, after the stress relaxation layer, the wiring, and the external electrode are formed on the wafer, the wafer is cut to obtain individual semiconductor devices. Therefore, since stress relaxation layers, wirings, and external electrodes can be simultaneously formed for many semiconductor devices, it is preferable in view of mass productivity.

As the stress relaxation layer, for example, a resin having a Young's modulus of 1 × 10 ¹⁰ Pa or less is used.

  In the step of providing the stress relaxation layer, the stress relaxation layer may be provided by applying a photosensitive resin to the wafer so as to include the electrode and removing a region corresponding to the electrode of the photosensitive resin. .

  The stress relaxation layer may be provided by printing a resin constituting the stress relaxation layer.

  The photosensitive resin may be one of polyimide, silicone, and epoxy.

The stress relaxation layer is provided by adhering a plate in which holes corresponding to the electrodes are formed to the wafer,
The plate may have a coefficient of thermal expansion between the semiconductor chip and a substrate on which the semiconductor chip is mounted.

  According to this, since the thermal expansion coefficient of the plate is a value between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the substrate, the stress can be relieved by the difference in the thermal expansion coefficient. Also, the plate used here is easier to form than a patterned substrate because it simply has holes.

  The stress relaxation layer may be made of a plate-shaped resin, and may be provided by bonding the plate-shaped resin to the wafer.

  According to this, unlike a patterned substrate, it can be easily formed into a predetermined shape.

  In the wafer used in the step of preparing the wafer, an insulating film may be formed in a region excluding the electrode and a region cut in the cutting step.

  You may have the process of roughening the surface of the said stress relaxation layer before the process of forming the said wiring.

After the step of forming the external electrode and before the step of cutting,
Applying a photosensitive resin to form a film until the external electrode is included in the formation surface of the external electrode; and
Performing isotropic etching until the external electrode is exposed to the photosensitive resin.

After the step of forming the external electrode and before the step of cutting,
You may have the process of apply | coating and forming an organic film until the said external electrode is included in the formation surface of the said external electrode.

  For the organic film, a flux may be used in which the residue changes into a thermoplastic polymer resin by a chemical reaction when heated.

  The wiring may be bent on the stress relaxation layer.

  In the connecting portion between the wiring and the electrode, the width of the wiring may be larger than the width of the electrode.

  In the present invention, the stress relaxation layer is formed, and the wiring is formed on the stress relaxation layer, and then a solder portion is formed on the wiring by electroless plating, and the solder portion is connected to the external portion. The electrode may be molded.

In the present invention, forming the stress relaxation layer and forming a conductive layer on the stress relaxation layer;
Forming a solder portion by electroplating on the conductive layer;
Processing the conductive layer into the wiring;
Forming the solder part into the external electrode;
May be included.

  The present invention may include a step of forming a protective film on the wiring in a region avoiding the external electrode.

  The solder portion may be formed on a pedestal formed at the wiring destination.

  The solder portion may be formed on a solder film formed by plating.

In the present invention, after the step of forming the wiring, a step of forming a protective film on the wiring;
Before the step of forming the external electrode, further comprising the step of forming an opening in at least a part of the protective film corresponding to the external electrode,
In the step of forming the external electrode, the external electrode may be formed by printing solder cream on the opening and performing wet back.

In the present invention, after the step of forming the wiring, a step of forming a protective film on the wiring;
Before the step of forming the external electrode, further comprising the step of forming an opening in at least a part of the protective film corresponding to the external electrode,
In the step of forming the external electrode, the external electrode may be formed by mounting a piece of solder in each opening after applying a flux in the opening.

  The protective film may be made of a photosensitive resin, and the opening may be formed including exposure and development processes.

  The present invention may include a step of disposing a protective member on the side surface of the wafer opposite to the surface having the electrode before cutting the wafer into individual pieces.

  By doing so, the back surface side of the semiconductor device is covered with the protective film, so that it can be prevented from being scratched.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bumps on one surface of a wafer,
Applying a resin on the surface until the bumps are included;
Performing isotropic dry etching on the surface of the resin;
Cutting the wafer into individual pieces;
Including
The dry etching process is completed before the bumps are exposed and the surfaces are exposed.

  According to the present invention, the resin is applied to one surface of the wafer. This resin is applied from above the bump, but since the bump protrudes from the surface, the resin is applied thinner on the bump than the other parts.

  Therefore, when isotropic dry etching is performed on the surface of the resin, the resin is evenly cut in all regions, so that a thin bump is first exposed. At this time, since the wafer surface is not exposed yet, the dry etching is finished here. In this way, it is possible to obtain a wafer in which the bumps are exposed and the areas other than the bumps are covered and protected by the resin.

  Thereafter, the wafer can be cut into individual pieces to obtain a semiconductor device.

An electronic component manufacturing method according to the present invention includes a step of integrally forming a plurality of electronic elements in a substrate shape,
Providing a stress relaxation layer in at least a region where the external electrode is formed in the substrate-like electronic element;
Forming the external electrode on the stress relaxation layer;
Cutting the substrate-like electronic element into individual pieces;
Have

  According to the present invention, since the stress absorption layer is provided, it is possible to absorb stress due to a difference in thermal expansion between the electronic component and the mounting substrate. Examples of the electronic component include a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a varistor, a volume, a fuse, and a semiconductor device.

An electronic component manufacturing method according to the present invention includes a step of forming a plurality of bumps on a mounting surface of an electronic element on a circuit board;
In the mounting surface, applying a resin until the bump is included;
Performing isotropic dry etching on the surface of the resin;
Including
The dry etching process is completed before the bumps are exposed and the mounting surface is exposed.

  According to the present invention, the resin is applied to the mounting surface of the electronic element. This resin is applied from above the bump, but since the bump protrudes from the mounting surface, the resin is applied thinner on the bump than the other parts.

  Therefore, when isotropic dry etching is performed on the surface of the resin, the resin is evenly cut in all regions, so that a thin bump is first exposed. At this time, since the mounting surface is not exposed yet, the dry etching is finished here. In this way, an electronic component can be obtained in which the bump is exposed and the mounting surface is protected by the resin while avoiding the bump.

  In the present invention, a semiconductor element may be used as the electronic element.

The method of manufacturing an electronic component according to the present invention includes a step of forming a plurality of bumps on one surface of an electronic element plate,
Applying a resin on the surface until the bumps are included;
Performing isotropic dry etching on the surface of the resin;
Cutting the electronic element plate into individual pieces;
Including
The dry etching process is completed before the bumps are exposed and the mounting surface is exposed.

  According to the present invention, the resin is applied to one surface of the electronic element plate. This resin is applied from above the bump, but since the bump protrudes from the surface, the resin is applied thinner on the bump than the other parts.

  Therefore, when isotropic dry etching is performed on the surface of the resin, the resin is evenly cut in all regions, so that a thin bump is first exposed. At this time, since the surface of the electronic element plate is not exposed yet, the dry etching is finished here. Thus, it is possible to obtain an electronic element plate in which the bumps are exposed and the areas other than the bumps are covered and protected by the resin.

  Then, after that, the electronic element plate can be cut into individual pieces to obtain a semiconductor device.

  The electronic component according to the present invention has the external electrode on the stress relaxation layer. For example, a semiconductor device can be given as an electronic component.

  The electronic component according to the present invention includes a plurality of bumps manufactured by the above method and formed on the mounting surface, and a resin that covers the mounting surface while avoiding at least an upper end portion of the bump.

A semiconductor device according to the present invention includes a semiconductor chip having an electrode,
A stress relaxation layer provided on the semiconductor chip so as to avoid at least a part of the electrode;
Wiring formed on the stress relaxation layer from the electrode;
An external electrode formed on the wiring above the stress relaxation layer;
Have

  The wiring includes aluminum, aluminum alloy, chrome, copper or gold layer, copper and gold bilayer, chrome and copper bilayer, chrome and gold bilayer, platinum and gold bilayer, and chrome, copper and It may be formed of any one of three gold layers.

  The wiring may be formed of a chrome layer formed on the stress relaxation layer and at least one of copper and gold.

  The wiring may include a titanium layer.

  Since titanium is excellent in moisture resistance, disconnection due to corrosion can be prevented. Titanium is also excellent in adhesiveness with a polyimide resin, and excellent in reliability when the stress relaxation layer is formed of a polyimide resin.

  The wiring may include one of nickel or two layers of platinum and gold formed on the titanium layer.

  In the semiconductor device, a protective film may be provided on a side surface of the semiconductor chip opposite to the surface having the electrode.

  The protective film may be made of a material different from the material used for the wafer and having a melting point equal to or higher than the melting temperature of the solder.

  In the semiconductor device, a heat radiator may be provided on a side surface opposite to the surface having the electrode of the semiconductor chip.

  The semiconductor device according to the present invention includes a plurality of bumps manufactured by the above method and formed on the mounting surface, and a resin that covers the mounting surface while avoiding at least an upper end portion of the bump.

The electronic component mounting method according to the present invention includes a step of applying a flux until a bump is included on a mounting surface having a plurality of bumps formed on an electronic element, and on the wiring of a circuit board via the flux. A reflow process performed after placing the bumps;
including.

  According to the present invention, since the flux is applied to the mounting surface, the flux covers and protects the mounting surface as it is even after the reflow process is completed. Moreover, the flux does not need to be applied so as to avoid the bumps, and is simply applied to the entire mounting surface including the bumps, so that it can be applied easily.

  In the present invention, a semiconductor element may be used as the electronic element.

  The semiconductor device is mounted on a circuit board according to the present invention.

  On the circuit board according to the present invention, the semiconductor device having a plurality of bumps formed on the mounting surface and a resin covering the mounting surface while avoiding at least the upper end portion of the bump is mounted.

  The electronic device according to the present invention has this circuit board.

  The electronic device according to the present invention includes a circuit board on which a semiconductor device having a plurality of bumps formed on the mounting surface and a resin that covers the mounting surface while avoiding at least an upper end portion of the bump is mounted.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 5 is a plan view showing the semiconductor device according to the present embodiment. This semiconductor device is classified as a so-called CSP. A wiring 3 is formed in the central direction of the active surface 1a from an electrode 12 formed in the peripheral portion of the semiconductor chip 1, and an external electrode 5 is provided in each wiring 3. Is provided. Since all the external electrodes 5 are provided on the stress relaxation layer 7, it is possible to alleviate stress when mounted on a circuit board (not shown). Further, a solder resist layer 8 is formed as a protective film in a region excluding the external electrode 5.

  The stress relaxation layer 7 is formed at least in a region surrounded by the electrode 12. The electrode 12 refers to a portion connected to the wiring 3, and this definition is the same in all the following embodiments. In consideration of securing a region for forming the external electrode 5, although not shown in FIG. 5, the stress relaxation layer 7 exists at a position on the outer periphery of the electrode 12, and the wiring 3 is routed thereon. Similarly, the external electrode 5 may be provided. The manufacturing process shown in FIGS. 1A to 4C to be described later is drawn assuming an example in which the stress relaxation layer 7 also exists around the electrode 12 shown in FIG.

  The electrode 12 is an example of a so-called peripheral electrode type located in the peripheral portion of the semiconductor chip 1, but an area array arrangement type semiconductor chip in which an electrode is formed in an inner region than the peripheral region of the semiconductor chip may be used. good. In this case, the stress relaxation layer may be formed so as to avoid at least a part of the electrode.

  As shown in the figure, the external electrode 5 is provided not on the electrode 12 of the semiconductor chip 1 but in an active region of the semiconductor chip 1 (region where active elements are formed). The external electrode 5 can be provided in the active region by providing the stress relaxation layer 7 in the active region and further disposing (withdrawing) the wiring 3 in the active region. Therefore, when the external electrode 5 is disposed, an active region, that is, a region as a fixed surface can be provided, and the degree of freedom of the setting position of the external electrode 5 is greatly increased.

Then, by bending the wiring 3 on the stress relaxation layer 7, the external electrodes 5 are provided so as to be arranged in a lattice pattern. Since this is not an essential configuration of the present invention, the external electrodes 5 do not necessarily have to be arranged in a grid pattern. Further, at the junction between the electrode 12 and the wiring 3, the width of the electrode 12 and the width of the wiring 3 shown in the drawing are as follows:
Wiring 3 <electrode 12
But
Electrode 12 ≦ Wiring 3
It is preferable that In particular,
Electrode 12 <Wiring 3
In this case, not only the resistance value of the wiring 3 is decreased, but also the strength is increased, so that disconnection is prevented.

  1A to 4C are views for explaining a method of manufacturing a semiconductor device according to the first embodiment. These figures correspond to the cross section taken along the line II of FIG. 5, but are shown as a state in which a stress relaxation layer further exists on the outer periphery of FIG. FIG. 1A to FIG. 4C are partially enlarged views of a wafer, and in particular, take up a portion corresponding to one when a semiconductor device is formed.

  First, the electrodes 12 and other elements are usually formed on the wafer 10 by a known technique until the state before dicing. In this example, the electrode 12 is made of aluminum. As another example, the electrode 12 may be made of an aluminum alloy material (for example, aluminum silicon or aluminum silicon copper) or a copper material.

  Further, a passivation film (not shown) made of an oxide film or the like is formed on the surface of the wafer 10 in order to prevent chemical changes. The passivation film is formed not only avoiding the electrode 12 but also avoiding a scribe line where dicing is performed. By not forming the passivation film on the scribe line, it is possible to avoid generation of dust generated by the passivation film during dicing, and to prevent generation of cracks in the passivation film.

  As shown in FIG. 1A, a photosensitive polyimide resin is applied to the wafer 10 having the electrodes 12 (for example, by “spin coating method”) to form a resin layer 14. The resin layer 14 is preferably formed in a thickness of 1 to 100 μm, more preferably about 10 μm. In the spin coating method, since a large amount of polyimide resin is wasted, a device that discharges the polyimide resin in a belt shape by a pump may be used. As such an apparatus, for example, there is an FAS ultra-precise discharge type coating system manufactured by FAS (see US Pat. No. 4,696,885). In addition, the resin layer 14 here has a function as the stress relaxation layer 7 (refer FIG. 5).

  As shown in FIG. 1B, a contact hole 14 a for the electrode 12 is formed in the resin layer 14. Specifically, the contact hole 14a is formed in the resin layer 14 by removing the polyimide resin from the vicinity of the electrode 12 by exposure, development, and baking. In the figure, there is no region where the resin layer 14 overlaps the electrode 12 when the contact hole 14a is formed. Although the resin layer 14 is not left on the electrode 12 at all, there is an advantage that an electrical contact with a metal such as a wiring provided in the subsequent process becomes good, but such a structure has to be necessarily provided. Do not mean. In other words, even if the resin layer 14 is in the vicinity of the outer periphery of the electrode 12, if the hole is formed so that a part of the electrode 12 is exposed, the object is sufficiently achieved. In this case, since the number of bends in the wiring layer is reduced, it is possible to prevent a decrease in wiring reliability due to disconnection or the like. Here, the contact hole 14a is tapered. Here, the taper refers to a state in which the thickness of the resin layer 14 decreases in the vicinity of the electrode 12 (contact portion) as it approaches the electrode 12. Accordingly, the resin layer 14 is inclined at the end where the contact hole 14a is formed. Such a shape is formed by setting exposure and development conditions. Furthermore, if the electrode 12 is plasma-treated with O 2 or CF 4 or the like, the polyimide resin can be completely removed even if a little polyimide resin remains on the electrode 12. The resin layer 14 thus formed becomes a stress relaxation layer in a semiconductor device as a finished product.

In this example, a photosensitive polyimide resin is used as the resin, but a non-photosensitive resin may be used. For example, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, or the like that has a low Young's modulus when solidified (1 × 10 ¹⁰ Pa or less) and can perform a stress relaxation function may be used. When a non-photosensitive resin is used, a predetermined shape is formed through a photo process using a photoresist thereafter.

  As shown in FIG. 1C, a chrome (Cr) layer 16 is formed on the entire surface of the wafer 10 by sputtering. A wiring is finally formed from the chrome (Cr) layer 16. The chrome (Cr) layer 16 is formed from the electrode 12 to the resin layer 14. Here, the material of the chrome (Cr) layer 16 was selected because of its good adhesion to the polyimide constituting the resin layer 14. Alternatively, considering crack resistance, aluminum alloy such as aluminum, aluminum silicon, aluminum copper, or copper alloy, or a metal having a spreadability (extension property) such as copper (Cu) or gold may be used. Alternatively, if titanium having excellent moisture resistance is selected, disconnection due to corrosion can be prevented. Titanium is preferable from the viewpoint of adhesion to polyimide, and titanium tungsten may be used.

  Considering the adhesion with the chrome (Cr) layer 16, it is preferable to roughen the surface of the resin layer 14 made of polyimide or the like. For example, the surface of the resin layer 14 can be roughened by performing dry treatment exposed to plasma (O 2, CF 4) or wet treatment with acid or alkali.

  Further, since the end of the resin layer 14 is inclined in the contact hole 14a, the chrome (Cr) layer 16 is similarly inclined in this region. The chrome (Cr) layer 16 becomes the wiring 3 (see FIG. 5) in the semiconductor device as a finished product, and also becomes a diffusion prevention layer for the polyimide resin when the layer is subsequently formed during the manufacturing. The diffusion preventing layer is not limited to chrome (Cr), and all the above-described wiring materials are effective.

  As shown in FIG. 1D, a photoresist is coated on the chrome (Cr) layer 16 to form a resist layer 18.

  As shown in FIG. 1E, a part of the resist layer 18 is removed by exposure, development, and baking. The remaining resist layer 18 is formed from the electrode 12 toward the center of the resin layer 14. Specifically, the remaining resist layer 18 is such that the resist layer 18 on one electrode 12 and the resist layer 18 on the other electrode 12 do not continue on the resin layer 14 (each in an independent state). It has become.

  Then, leaving only the region covered with the resist layer 18 shown in FIG. 1E (that is, using the resist layer 18 as a mask), the chrome (Cr) layer 16 is etched, and the resist layer 18 is peeled off. As described above, the metal thin film forming technique in the wafer process is applied to these pre-processes. The chrome (Cr) layer 16 thus etched is as shown in FIG. 2A.

  In FIG. 2A, the chrome (Cr) layer 16 is formed from the electrode 12 to the resin layer 14. Specifically, the chrome (Cr) layer 16 is not continuous between one electrode 12 and another electrode 12. That is, the chrome (Cr) layer 16 is formed so that wiring corresponding to each electrode 12 can be configured. Note that the electrodes 12 do not necessarily have to be independent of each other as long as the same signal is input and output, and wirings that transmit the same signal may be electrically integrated.

  As shown in FIG. 2B, a copper (Cu) layer 20 is formed on the uppermost layer including at least the chrome (Cr) layer 16 by sputtering. The copper (Cu) layer 20 serves as a base layer for forming external electrodes. Alternatively, a nickel (Ni) layer may be formed instead of the copper (Cu) layer 20.

  A resist layer 22 (photoresist) is formed on the copper (Cu) layer 20 as shown in FIG. 2C, and a part of the resist layer 22 is removed by exposure, development and baking as shown in FIG. 2D. . Then, the region to be removed is at least part of the resist layer 22 located above the resin layer 14 and above the chrome (Cr) layer 16.

  As shown in FIG. 2E, a pedestal 24 is formed in a region where the resist layer 22 has been partially removed. The base 24 is formed by copper (Cu) plating, and a solder ball is formed thereon. Accordingly, the pedestal 24 is formed on the copper (Cu) layer 20 and is electrically connected to the electrode 12 through the copper (Cu) layer 20 and the chrome (Cr) layer 16.

  As shown in FIG. 3A, on the base 24, a solder 26 that becomes a solder ball as the external electrode 5 (see FIG. 5) is formed in a thick layer. Here, the thickness is determined by the amount of solder corresponding to the ball diameter required at the time of subsequent solder ball formation. The layer of the solder 26 is formed by electrolytic plating or printing.

  As shown in FIG. 3B, the resist layer 22 shown in FIG. 3A is stripped, and the copper (Cu) layer 20 is etched. Then, the base 24 becomes a mask, and the copper (Cu) layer 20 remains only under the base 24 (see FIG. 3C). Then, the solder 26 on the pedestal 24 is formed into a hemispherical ball or more by wet back to form a solder ball (see FIG. 3D). Here, wet back refers to forming a substantially hemispherical bump by reflowing after a solder material is formed at an external electrode formation position.

  A solder ball as the external electrode 5 (see FIG. 5) is formed by the above process. Subsequently, a process for preventing the oxidation of the chromium (Cr) layer 16 and the like, improving the moisture resistance of the completed semiconductor device, and achieving the objectives such as mechanical protection of the surface is shown in FIGS. 4A and 4B. This is done as shown in

  As shown in FIG. 4A, a photosensitive solder resist layer 28 is formed on the entire surface of the wafer 10 by coating. Then, exposure, development, and baking are performed to remove a portion of the solder resist layer 28 that covers the solder 26 and a region in the vicinity thereof. Thus, the remaining solder resist layer 28 serves as an antioxidant film, as a protective film when finally becoming a semiconductor device, and further as a protective film for the purpose of improving moisture resistance. Then, the electrical characteristics are inspected, and if necessary, the product number, manufacturer name, etc. are printed.

  Subsequently, dicing is performed to cut into individual semiconductor devices as shown in FIG. 4C. Here, the position where the dicing is performed (scribe line) is a position where the resin layer 14 is avoided, as is clear by comparing FIG. 4B and FIG. 4C. Therefore, dicing is performed only on the wafer 10 in which no passivation film or the like is present, so that a problem in cutting a plurality of layers made of materials having different properties can be avoided. The dicing process is performed by a conventional method. 4A and 4B show the middle part of the resin layer 14 located outside the electrode, but FIG. 4C shows the scribe line beyond the resin layer 14 located outside the electrode. ing.

  According to the semiconductor device thus formed, the resin layer 14 becomes the stress relaxation layer 7 (see FIG. 5), so that the thermal expansion coefficient between the circuit board (not shown) and the semiconductor chip 1 (see FIG. 5). The stress due to the difference is relaxed.

  According to the semiconductor device manufacturing method described above, almost all the steps are completed in the wafer process. In other words, the process of forming the external terminals connected to the mounting substrate can be performed within the wafer process, and the conventional packaging process, that is, the individual semiconductor chips are handled and the inner lead bonding is performed on each individual semiconductor chip. It is not necessary to perform a process, an external terminal formation process, etc. Further, when the stress relaxation layer is formed, a substrate such as a patterned film becomes unnecessary. For these reasons, a low-cost and high-quality semiconductor device can be obtained.

  In this example, two or more wiring layers may be provided. If the layers are stacked, the layer thickness generally increases and the wiring resistance can be lowered. In particular, when one of the wirings is made of chrome (Cr), copper (Cu) or gold has a lower electrical resistance than chrome (Cr), so that the wiring resistance can be lowered by combining them. Alternatively, a titanium layer may be formed on the stress relaxation layer, and a nickel layer or a layer made of platinum and gold may be formed on the titanium layer. Alternatively, two layers of platinum and gold may be used as the wiring.

(Second Embodiment)
6A to 7C are views for explaining a method of manufacturing a semiconductor device according to the second embodiment. The present embodiment differs from the first embodiment in the steps after FIG. 3A, and the steps up to FIG. 2E are the same as those in the first embodiment. Therefore, the wafer 110, the electrode 112, the resin layer 114, the chrome (Cr) layer 116, the copper (Cu) layer 120, the resist layer 122, and the pedestal 124 shown in FIG. 6A are the same as the wafer 10, the electrode 12, and the resin layer shown in FIG. 2E. 14, the chrome (Cr) layer 16, the copper (Cu) layer 20, the resist layer 22 and the pedestal 124, and the manufacturing method is the same as that shown in FIGS.

  In this embodiment, as shown in FIG. 6A, thin solder 126 is plated on the pedestal 124, and the resist layer 122 is peeled off, as shown in FIG. 6B. Further, using the thin solder 126 as a resist, the copper (Cu) layer 120 is etched as shown in FIG. 6C.

  Subsequently, as shown in FIG. 7A, a photosensitive solder resist layer 128 is formed on the entire surface of the wafer 110, and as shown in FIG. 7B, the solder resist layer 128 in the region of the pedestal 124 is removed by exposure, development, and baking. To do.

  Then, as shown in FIG. 7C, a thick solder 129 thicker than the thin solder 126 is plated on the base 124 where the thin solder 126 remains. This is done by electroless plating. The thick solder 129 is then formed into a hemispherical or more ball shape by wet back as in the state shown in FIG. Thus, the thick solder 129 becomes a solder ball as the external electrode 5 (see FIG. 5). The subsequent steps are the same as those in the first embodiment described above. Alternatively, the thin solder 126 and the thick solder 129 may be plated in this order, and then a photosensitive solder resist layer (step of FIG. 7A) may be performed.

  Also according to this embodiment, almost all steps can be performed in the wafer process. In the present embodiment, the thick solder 129 is formed by electroless plating. Therefore, the pedestal 124 can be omitted, and the thick solder 129 can be formed directly on the copper (Cu) layer 120.

(Third embodiment)
8A to 9D are views for explaining a method for manufacturing a semiconductor device according to the third embodiment.

  The wafer 30, the electrode 32, the resin layer 34, the chrome (Cr) layer 36, the copper (Cu) layer 40, and the resist layer 42 shown in FIG. 8A are the same as the wafer 10, the electrode 12, the resin layer 14, and the chrome (Cr ) Layer 16, copper (Cu) layer 20, and resist layer 22, and the manufacturing method is the same as that shown in FIGS.

  Then, a part of the resist layer 42 shown in FIG. 8A is removed by exposure, development and baking. Specifically, as shown in FIG. 8B, the resist layer 42 at other positions is removed, leaving only the resist layer 42 located above the chrome (Cr) layer 36 to be a wiring.

  Subsequently, the copper (Cu) layer 40 is etched to peel off the resist layer 42, leaving the copper (Cu) layer 40 only on the chrome (Cr) layer 36, as shown in FIG. 8C. Thus, a wiring having a two-layer structure of the chrome (Cr) layer 36 and the copper (Cu) layer 40 is formed.

  Next, as shown in FIG. 8D, a photosensitive solder resist is applied to form a solder resist layer 44.

  As shown in FIG. 9A, contact holes 44 a are formed in the solder resist layer 44. The contact hole 44a is formed above the resin layer 34 and on the copper (Cu) layer 40 that is the surface layer of the wiring having a two-layer structure. The contact hole 44a is formed by exposure, development, and baking. Or you may print a soldering resist, providing a hole in a predetermined position so that the contact hole 44a may be formed.

  Subsequently, the solder cream 46 is printed in the contact hole 44a so as to form a raised shape (see FIG. 9B). The solder cream 46 becomes a solder ball by wet back as shown in FIG. 9C. Then, dicing is performed to obtain individual semiconductor devices shown in FIG. 9D.

  In the present embodiment, the solder ball pedestal is omitted, and the printing of solder cream is applied, so that the formation of the solder ball is facilitated and the manufacturing process is reduced.

  Moreover, the wiring of the semiconductor device to be manufactured has two layers of chromium (Cr) and copper (Cu). Here, chrome (Cr) has good adhesion to the resin layer 34 made of polyimide resin, and copper (Cu) has good crack resistance. Since the crack resistance is good, it is possible to prevent disconnection of the wiring or damage to the electrode 32 or the active element. Alternatively, the wiring may be constituted by two layers of copper (Cu) and gold, two layers of chromium and gold, or three layers of chromium, copper (Cu) and gold.

  In the present embodiment, an example without a pedestal is given, but it goes without saying that a pedestal may be provided.

(Fourth embodiment)
FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.

  The wafer 130, the electrode 132, the resin layer 134, the chrome (Cr) layer 136, the copper (Cu) layer 140, and the solder resist layer 144 shown in the figure are the same as the wafer 30, the electrode 32, the resin layer 34, and the chrome (shown in FIG. 9A). The method is the same as that of the (Cr) layer 36, the copper (Cu) layer 40, and the solder resist layer 44, and the manufacturing method is the same as that shown in FIGS.

  In this embodiment, instead of using the solder cream 46 in FIG. 9B, solder balls 148 are mounted by applying flux 146 to the contact holes 144 a formed in the solder resist layer 144. Thereafter, wetback, inspection, marking, and dicing processes are performed.

  According to the present embodiment, a pre-formed solder ball 148 is mounted and used as the external electrode 5 (see FIG. 5). Further, the pedestals 24 and 124 can be omitted as compared with the first and second embodiments. Furthermore, the wiring 3 (see FIG. 5) has a two-layer structure of a chrome (Cr) layer 136 and a copper (Cu) layer 140.

  In the present embodiment, an example without a pedestal is given, but it goes without saying that a pedestal may be provided.

(Fifth embodiment)
11A to 12C are views for explaining a method for manufacturing a semiconductor device according to the fifth embodiment.

  First, as shown in FIG. 11A, a glass plate 54 is bonded to a wafer 50 having electrodes 52. A hole 54 a corresponding to the electrode 52 of the wafer 50 is formed in the glass plate 54, and an adhesive 56 is applied.

  The thermal expansion coefficient of the glass plate 54 is a value between the thermal expansion coefficient of the wafer 50 serving as a semiconductor chip and the thermal expansion coefficient of the circuit board on which the semiconductor device is mounted. From this, the value of the thermal expansion coefficient changes in the order of the semiconductor chip obtained by dicing the wafer 50, the glass plate 54, and the circuit board (not shown) on which the semiconductor device is mounted. The difference between the two becomes smaller and the thermal stress becomes smaller. That is, the glass plate 54 becomes a stress relaxation layer. A ceramic plate may be used instead of the glass plate 54 as long as it has a similar thermal expansion coefficient.

  When the glass plate 54 is bonded to the wafer 50, the adhesive 56 that has entered the hole 54 is removed by O2 plasma treatment, as shown in FIG. 11B.

  Next, as shown in FIG. 11C, an aluminum layer 58 is formed on the entire surface of the wafer 50 and on the glass plate 54 by sputtering. Thereafter, if a film is formed on the surface of the hole 54, it is possible to protect aluminum which is relatively easily broken. Next, a resist layer 59 is formed as shown in FIG. 12A, and as shown in FIG. 12B, a part of the resist layer 59 is removed by exposure, development, and baking treatment. The resist layer 59 to be removed is preferably at a position other than the wiring pattern forming portion.

  In FIG. 12B, the resist layer 59 is left from above the electrode 52 to above the glass plate 54. Further, there is an interruption so that the upper part of one electrode 52 and the upper part of the other electrode 52 are not continuous.

  When the aluminum layer 58 is etched, as shown in FIG. 12C, the aluminum layer 58 remains in a region to be a wiring. That is, the aluminum layer 58 is formed as a wiring from the electrode 52 to the glass plate 54. In addition, an aluminum layer 58 is formed so that the electrodes 52 are not connected to each other and become wiring for each electrode 52. Alternatively, if it is necessary to make the plurality of electrodes 52 conductive, an aluminum layer 58 serving as a wiring may be formed correspondingly. In addition to the aluminum layer 58, any of the materials selected in the first embodiment can be applied as the wiring.

  Since the wiring from the electrode 52 is formed by the above steps, solder balls are formed on the aluminum layer 58 as the wiring, and the wafer 50 is cut into individual semiconductor devices. These steps can be performed in the same manner as in the first embodiment.

  According to this embodiment, although the glass plate 54 has the hole 54a, the formation of the hole 54a is easy. Therefore, it is not necessary to pattern the glass plate 54 so as to form bumps and wirings in advance. In addition, the metal thin film forming technique in the wafer process is applied to the formation process of the aluminum layer 58 and the like to be the wiring, and almost all processes are completed by the wafer process.

  Note that another stress absorbing layer such as a polyimide resin may be further provided on the glass plate 54 as in the first embodiment. In this case, since the stress absorption layer is newly provided, the thermal expansion coefficient of the glass plate 54 may be equal to that of silicon.

(Sixth embodiment)
13A to 13D are views for explaining a method for manufacturing a semiconductor device according to the sixth embodiment. In this example, a polyimide plate previously formed in a plate shape was selected as the stress relaxation layer. In particular, since polyimide has a composition with a low Young's modulus, that composition was selected as the stress relaxation layer. In addition, for example, a composite plate such as a plastic plate or a glass epoxy type may be used. In this case, it is preferable to use the same material as the mounting substrate because there is no difference in thermal expansion coefficient. In particular, since there are many plastic substrates as mounting substrates today, it is effective to use a plastic plate for the stress relaxation layer.

  First, as shown in FIG. 13A, a polyimide plate 64 is bonded to a wafer 60 having an electrode 62 so as to be shown in FIG. 13B. The polyimide plate 64 is pre-coated with an adhesive 66. It is more preferable to select a material that gives the adhesive 66 a stress relaxation function. Specific examples of the adhesive having a stress relaxation function include thermoplastic polyimide resins and silicone resins.

  Next, as shown in FIG. 13C, a contact hole 64a is formed in the region corresponding to the electrode 62 using an excimer laser or the like, and as shown in FIG. 13D, an aluminum layer 68 is formed by sputtering. In addition to the aluminum layer 68, any of the materials selected in the first embodiment can be applied.

  Thus, since the state is the same as that in FIG. 11C, the semiconductor device can be manufactured by performing the steps in FIG. 12A and thereafter.

  According to this embodiment, since the polyimide plate 64 in which no holes are formed is used, a patterned substrate becomes unnecessary. Other effects are the same as those in the first to fifth embodiments.

  As another form, a drilling process or the like may be performed in advance on the stress relaxation layer to provide a hole, and thereafter, an arrangement process such as bonding to the wafer may be performed. In addition to machining, holes can be provided by chemical etching or dry etching. In addition, when forming a hole using chemical etching or dry etching, it may be performed on the wafer or in a previous preliminary process.

(Seventh embodiment)
14A to 17C are views for explaining a method of manufacturing a semiconductor device according to the seventh embodiment, and correspond to a cross section taken along line II in FIG. FIG. 18 is a diagram illustrating a semiconductor device according to the seventh embodiment.

  In the present embodiment, the step of exposing the bump 205 from the solder resist layer 228 (see FIGS. 17A and 17B) is more specifically shown than in the first embodiment. Other contents are the same as in the first embodiment.

  First, an electrode 212 and other elements are formed on the wafer 210 by a known technique, and a photosensitive polyimide resin is applied to the wafer 210 having the electrode 212 to form a resin layer 214 as shown in FIG. 14A. To do. A passivation film is formed on the surface of the wafer 210 while avoiding the electrode 212 and the scribe line.

  As shown in FIG. 14B, a contact hole 214 a for the electrode 212 is formed in the resin layer 214.

  As shown in FIG. 14C, a chrome (Cr) layer 216 is formed on the entire surface of the wafer 210 by sputtering.

  As shown in FIG. 14D, a photoresist layer 218 is formed on the chrome (Cr) layer 216 by applying a photoresist.

  As shown in FIG. 14E, a part of the resist layer 218 is removed by exposure, development, and baking. The remaining resist layer 218 is formed from the electrode 212 toward the center of the resin layer 214.

  Then, the chrome (Cr) layer 216 is etched leaving only the region covered with the resist layer 218 shown in FIG. 14E, and the resist layer 218 is peeled off. The chrome (Cr) layer 216 thus etched is as shown in FIG. 15A.

  In FIG. 15A, the chrome (Cr) layer 216 is formed from the electrode 212 to the resin layer 214.

  As shown in FIG. 15B, a copper (Cu) layer 220 is formed on the uppermost layer including at least the chromium (Cr) layer 216 by sputtering.

  A resist layer 222 is formed on the copper (Cu) layer 220 as shown in FIG. 15C, and a part of the resist layer 222 is removed by exposure, development and baking as shown in FIG. 15D. Then, the region to be removed is at least part of the resist layer 222 located above the resin layer 214 and above the chrome (Cr) layer 216.

  As shown in FIG. 15E, a pedestal 224 is formed in a region where the resist layer 222 has been partially removed. The pedestal 224 is formed by copper (Cu) plating, and a solder ball is formed thereon. Accordingly, the pedestal 224 is formed on the copper (Cu) layer 220 and is electrically connected to the electrode 212 through the copper (Cu) layer 20 and the chrome (Cr) layer 216.

  As shown in FIG. 16A, a solder 226 for forming solder balls as bumps 205 (see FIG. 18) is formed on the pedestal 224 in a thick layer. The thickness is determined by the amount of solder corresponding to the ball diameter required at the time of subsequent solder ball formation. The solder 226 layer is formed by electrolytic plating or printing.

  As shown in FIG. 16B, the resist layer 222 shown in FIG. 16A is removed, and the copper (Cu) layer 220 is etched. Then, the pedestal 224 serves as a mask, and the copper (Cu) layer 220 remains only under the pedestal 224 (see FIG. 16C). Then, the solder 226 on the pedestal 224 is formed into a hemispherical ball or more by wet back to form a solder ball (see FIG. 16D).

  A solder ball as a bump 205 (see FIG. 18) is formed by the above process. Subsequently, treatments for preventing the oxidation of the chromium (Cr) layer 216 and the like, improving the moisture resistance of the completed semiconductor device, and achieving the objectives such as mechanical protection of the surface are shown in FIGS. 17A and 17B. This is done as shown in

  As shown in FIG. 17A, a solder resist layer 228 is formed on the entire surface of the wafer 210 by applying a resin (such as spin coating or drip).

  In the present embodiment, the solder resist layer 228 is also formed on the bump 205. That is, the solder resist layer 228 may be formed on the entire surface of the wafer 210, and it is not necessary to form the solder resist layer 228 while avoiding the bump 205. Therefore, a simple coating process is sufficient.

  Here, when a resin is applied to one surface including the bump 205 and then formed into a film by, for example, curing thereafter, the photosensitive resin applied to the bump 205 flows on the surface of the wafer 210 as shown in FIG. 17A. Therefore, the thickness of the solder resist layer 228 becomes different. That is, the solder resist layer 228 formed on the surface of the bump 205 is thin, and the solder resist layer 228 formed on the other wafer surface 10 is thick.

  Therefore, dry etching is performed on such a solder resist layer 228. In particular, isotropic etching that is common as dry etching is performed. Then, as shown in FIG. 17B, when the thin solder resist layer 228 on the bump 205 is removed by etching, the etching process is finished. At this time, the thick solder resist layer 228 on the wafer 210 remains. In this way, the solder resist layer 228 can be left on the wafer 210 while avoiding the bump 205, and this solder resist layer 228 becomes a protective layer. That is, the remaining solder resist layer 228 serves as an antioxidant film, as a protective film when finally becoming a semiconductor device, and further as a protective film for the purpose of improving moisture resistance. Then, the electrical characteristics are inspected, and if necessary, the product number, manufacturer name, etc. are printed.

  According to the above process, the lithography process of the solder resist layer 228 becomes unnecessary, and the cost can be reduced by simplifying the process.

  Subsequently, dicing is performed to cut the wafer 210 into semiconductor chips 201 as shown in FIG. 17C. Here, the position where dicing is performed is a position where the resin layer 214 is avoided, as is clear by comparing FIG. 17B and FIG. 17C. Therefore, since dicing is performed only on the wafer 210, problems when cutting a plurality of layers made of materials having different properties can be avoided. The dicing process is performed by a conventional method.

  According to the semiconductor device 200 thus formed, since the resin layer 214 becomes the stress relaxation layer 207 (see FIG. 18), thermal expansion between the circuit board (not shown) and the semiconductor chip 201 (see FIG. 18). Stress due to the difference in coefficients is relieved.

  FIG. 18 is a plan view showing the semiconductor device according to the present embodiment. This semiconductor device 200 is classified as a so-called CSP. A wiring 3 is formed from the electrode 212 of the semiconductor chip 201 toward the center of the active surface 201a, and a bump 205 is provided on each wiring 203. Since all the bumps 205 are provided on the stress relaxation layer 207, it is possible to relieve stress when mounted on a circuit board (not shown). A solder resist layer 228 is formed on the wiring 203 as a protective film.

  In the above embodiment, since the semiconductor device is manufactured by performing almost all the steps in the wafer process, the formation of the solder resist layer 228 as the protective layer is also performed in the wafer process. However, the present invention is not limited to this. Absent. For example, the resin may be applied to one surface of the semiconductor device including the bump, and the resin may be removed from the bump by performing isotropic dry etching.

(Eighth embodiment)
FIG. 19A and FIG. 19B are diagrams for explaining a semiconductor device mounting method according to the eighth embodiment. Here, the semiconductor device 300 has the same configuration as the semiconductor device 200 shown in FIG. 17C except that the flux layer 232 is formed on the bump 230. That is, the wiring 238 is drawn from the electrode 236 of the semiconductor chip 234 and the pitch is changed, and the bump 230 is formed on the wiring 238. Further, since the wiring 238 is formed on the stress relaxation layer 240, the stress applied to the bump 230 can be relaxed.

  Here, the flux layer 232 is formed by applying the flux to one surface with the bumps 230 of the semiconductor device 300 facing upward. This application is performed by spin coating or drip. Moreover, it is preferable to use what changes a residue into a thermoplastic polymer resin by a chemical reaction when heated (for example, NS-501 by Nippon Superior Co., Ltd.). According to this, since the residue is chemically stable, it is not ionized and has excellent insulating properties.

  A semiconductor device 300 having such a flux layer 232 is mounted on a circuit board 250 as shown in FIG. 19A.

  Specifically, as shown in FIG. 19B, the bumps 230 are positioned on the wirings 252 and 254 of the circuit board 250 via the flux layer 232, and the semiconductor device 300 is mounted.

  Then, the solder for forming the bump 230 is melted by the reflow process, and the bump 230 and the wirings 252 and 254 are connected. The flux layer 232 is consumed in this soldering. However, the flux layer 232 is consumed only in the vicinity of the bump 230, and the flux layer 232 remains in other regions. Since the remaining flux layer 232 is heated in the reflow process, as described above, it becomes a thermoplastic polymer resin and is a layer having excellent insulating properties. Therefore, the residue of the flux layer 232 becomes a protective layer on the surface of the semiconductor device 300 on which the bumps 230 are formed.

  As described above, according to the present embodiment, the step of applying the flux also serves as the step of forming the protective layer, so that the step of forming the protective layer to which lithography or the like is applied becomes unnecessary.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the present invention is applied to a semiconductor device, but the present invention can be applied to various electronic components for surface mounting regardless of whether they are active components or passive components. Examples of the electronic component include a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a varistor, a volume, or a fuse.

(Other embodiments)
The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the present invention is applied to a semiconductor device, but the present invention can be applied to various electronic components for surface mounting regardless of whether they are active components or passive components.

  FIG. 20 is a diagram showing an example in which the present invention is applied to an electronic component for surface mounting. The electronic component 400 shown in the figure is provided with electrodes 404 on both sides of the chip portion 402, and is, for example, a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a varistor, a volume, or a fuse. Similar to the above-described embodiment, a wiring 408 is formed on the electrode 404 via a stress relaxation layer 406. A bump 410 is formed on the wiring 408.

  FIG. 21 is also a diagram showing an example in which the present invention is applied to an electronic component for surface mounting. The electrode 424 of the electronic component 420 is formed on the surface on the mounting side of the chip portion 422, and the stress relaxation layer 426. A wiring 428 is formed via the. Bumps 430 are formed on the wiring 428.

  In addition, since the manufacturing method of these electronic components 400 and 420 is the same as that of the said embodiment, description is abbreviate | omitted. The effect obtained by forming the stress relaxation layers 406 and 426 is the same as that of the above-described embodiment.

  Next, FIG. 22 is a diagram showing an example in which a protective layer is formed on a semiconductor device to which the present invention is applied. A semiconductor device 440 illustrated in FIG. 4 is obtained by forming a protective layer 442 on the semiconductor device illustrated in FIG. 4C, and is the same as the semiconductor device illustrated in FIG. 4C except for the protective layer 442.

  In the semiconductor device 440, the protective layer 442 is formed on the surface opposite to the mounting side, that is, the back surface. By doing so, it is possible to prevent the back surface from being scratched.

  Furthermore, it is possible to prevent damage to the semiconductor chip itself due to cracks originating from scratches on the back surface.

  The protective layer 442 is preferably formed on the back surface of the wafer before being cut into individual semiconductor devices 440. Thus, the protective layer 442 can be formed on the plurality of semiconductor devices 440 at the same time. Specifically, it is preferable to form the protective layer 442 on the wafer after all the metal thin film forming steps are completed. By carrying out like this, a metal thin film formation process can be performed smoothly.

  The protective layer 442 is preferably made of a material that can withstand high temperatures in the reflow process of the semiconductor device 440. Specifically, it is preferable to withstand the melting temperature of the solder. That is, it is preferable to use a material having a melting temperature equal to or higher than the melting temperature of solder for the protective layer 442. Further, for example, a resin may be used as the protective layer 442. In this case, the protective layer 442 may be formed by applying a resin used for the potting resin. Alternatively, the protective layer 442 may be formed by attaching a sticky or adhesive sheet. This sheet may be organic or inorganic.

  In this way, since the surface of the semiconductor device is covered with a substance other than silicon, the marking property is improved, for example.

  Next, FIG. 23 is a diagram showing an example in which a radiator is attached to a semiconductor device to which the present invention is applied. A semiconductor device 450 shown in the figure is obtained by attaching a heat radiator 452 to the semiconductor device shown in FIG. 4C. Except for the heat radiator 452, the semiconductor device 450 is the same as the semiconductor device shown in FIG.

  The heat radiator 452 is attached to the surface opposite to the mounting side, that is, the back surface of the semiconductor device 450 via a heat conductive adhesive 454. By doing so, heat dissipation is improved. The radiator 452 has a large number of fins 456 and is often formed of copper, copper alloy, aluminum nitride, or the like. In this example, the case with fins is taken as an example. However, even if a simple plate-like radiator (heat radiating plate) having no fins is attached, a corresponding heat radiation effect can be obtained. In this case, since it is a simple plate-like attachment, handling is easy and cost can be reduced.

  In the above embodiment, solder bumps and gold bumps are provided in advance on the semiconductor device side as external terminals. However, as another example, a pedestal such as copper is used as an external terminal without using solder bumps or gold bumps on the semiconductor device side. It may be used. In this case, it is necessary to provide solder in advance at the junction (land) of the mounting substrate (motherboard) on which the semiconductor device is mounted before mounting the semiconductor device.

  Moreover, it is preferable that the polyimide resin used in the said embodiment is black. By using the black polyimide resin as the stress relaxation layer, it is possible to avoid malfunction when the semiconductor chip receives light, and to improve light resistance and improve the reliability of the semiconductor device.

  FIG. 24 shows a circuit board 1000 on which an electronic component 1100 such as a semiconductor device manufactured by the method according to the above-described embodiment is mounted. As an electronic device including the circuit board 1000, a notebook personal computer 1200 is shown in FIG.

1A to 1E are views for explaining a method of manufacturing a semiconductor device according to the first embodiment. 2A to 2E are views for explaining the method of manufacturing the semiconductor device according to the first embodiment. 3A to 3D are views for explaining the method for manufacturing the semiconductor device according to the first embodiment. 4A to 4C are views for explaining a method of manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a plan view showing the semiconductor device according to the first embodiment. 6A to 6C are views for explaining a method of manufacturing a semiconductor device according to the second embodiment. 7A to 7C are views for explaining a method of manufacturing a semiconductor device according to the second embodiment. 8A to 8D are views for explaining a method for manufacturing a semiconductor device according to the third embodiment. 9A to 9D are views for explaining a method for manufacturing a semiconductor device according to the third embodiment. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment. 11A to 11C are views for explaining a method for manufacturing a semiconductor device according to the fifth embodiment. 12A to 12C are views for explaining a method of manufacturing a semiconductor device according to the fifth embodiment. 13A to 13D are views for explaining a method for manufacturing a semiconductor device according to the sixth embodiment. 14A to 14E are views for explaining the method for manufacturing a semiconductor device according to the seventh embodiment. 15A to 15E are views for explaining a method for manufacturing a semiconductor device according to the seventh embodiment. 16A to 16D are views for explaining a method for manufacturing a semiconductor device according to the seventh embodiment. FIG. 17A to FIG. 17C are diagrams for explaining the method of manufacturing a semiconductor device according to the seventh embodiment. FIG. 18 is a plan view showing a semiconductor device according to the seventh embodiment. FIG. 19A and FIG. 19B are diagrams for explaining a semiconductor device mounting method according to the eighth embodiment. FIG. 20 is a diagram showing an example in which the present invention is applied to an electronic component for surface mounting. FIG. 21 is a diagram showing an example in which the present invention is applied to an electronic component for surface mounting. FIG. 22 is a diagram showing an example in which a protective layer is formed on a semiconductor device to which the present invention is applied. FIG. 23 is a diagram showing an example in which a radiator is attached to a semiconductor device to which the present invention is applied. FIG. 24 is a diagram showing a circuit board on which electronic parts manufactured by applying the method according to the present invention are mounted. FIG. 25 is a diagram showing an electronic apparatus including a circuit board on which an electronic component manufactured by applying the method according to the present invention is mounted.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 3 ... Wiring, 5 ... External electrode, 7 ... Stress relaxation layer, 8 ... Solder resist layer, 10 ... Wafer, 12 ... Electrode, 14 ... Resin layer, 18 ... Resist layer, 22 ... Resist layer, 24 Pedestal, 26 ... solder, 28 ... solder resist layer, 32 ... electrode, 34 ... resin layer, 42 ... resist layer, 44 ... solder resist layer, 46 ... solder cream, 50 ... wafer, 52 ... electrode, 54 ... glass plate 56 ... Adhesive, 58 ... Aluminum layer, 59 ... Resist layer, 60 ... Wafer, 62 ... Electrode, 64 ... Polyimide plate, 66 ... Adhesive, 68 ... Aluminum layer, 110 ... Wafer, 122 ... Resist layer, 124 ... Pedestal, 126 ... Thin solder, 128 ... Photosensitive solder resist layer, 128 ... Solder resist layer, 129 ... Thickness C 144: Solder resist layer, 146: Flux, 148 ... Solder ball, 200 ... Semiconductor device, 201 ... Semiconductor chip, 203 ... Wiring, 205 ... Bump, 207 ... Stress relaxation layer, 210 ... Wafer, 212 ... Electrode, 214 ... resin layer, 218 ... resist layer, 222 ... resist layer, 224 ... pedestal, 226 ... solder, 228 ... solder resist layer, 230 ... bump, 232 ... flux layer, 234 ... semiconductor chip, 236 ... electrode, 238 ... wiring, DESCRIPTION OF SYMBOLS 240 ... Stress relaxation layer, 250 ... Circuit board, 300 ... Semiconductor device, 400 ... Electronic component, 402 ... Chip part, 404 ... Electrode, 406 ... Stress relaxation layer, 408 ... Wiring, 410 ... Bump, 420 ... Electronic component, 422 ... chip part, 424 ... electrode, 426 ... stress relaxation Layers, 428 ... wire, 430 ... bumps, 440 ... semiconductor device, 442 ... protective layer, 450 ... semiconductor device, 452 ... radiator, 454 ... heat-conductive adhesive, 456 ... fin

Claims (19)

Preparing a wafer on which electrodes are formed;
Providing a stress relaxation layer on the wafer so as to avoid at least a portion of the electrode;
Forming a wiring from the electrode to the stress relaxation layer;
Forming an external electrode made of solder connected to the wiring above the stress relaxation layer;
Applying a resin to form a surface of the external electrode so as to be in contact with the wiring and including the external electrode;
A process of isotropic etching until the external electrode is exposed to the film-formed resin so that the film-formed resin remains on the wafer while avoiding the external electrode;
Cutting the wafer into individual pieces;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein a resin having a Young's modulus of 1 × 10 ¹⁰ Pa or less is used as the stress relaxation layer. In the manufacturing method of the semiconductor device according to claim 1,
In the step of providing the stress relaxation layer, a photosensitive resin is applied to the wafer so as to include the electrode, and a region corresponding to the electrode of the photosensitive resin is removed to provide the stress relaxation layer. Production method. In the manufacturing method of the semiconductor device according to claim 1,
The said stress relaxation layer is a manufacturing method of the semiconductor device provided by printing resin which comprises this stress relaxation layer. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the photosensitive resin is any one of polyimide, silicone, and epoxy. In the manufacturing method of the semiconductor device according to claim 1,
The stress relaxation layer is provided by adhering a plate in which holes corresponding to the electrodes are formed to the wafer,
The said board is a manufacturing method of the semiconductor device which has a thermal expansion coefficient between the said wafer and the board | substrate with which the said piece cut | disconnected from the said wafer is mounted. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the stress relaxation layer is made of a plate-shaped resin and is provided by bonding the plate-shaped resin to the wafer. In the manufacturing method of the semiconductor device according to claim 1,
The wafer used in the step of preparing the wafer is a method of manufacturing a semiconductor device in which an insulating film is formed in a region excluding the electrode and a region cut in the cutting step. The method of manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, comprising a step of roughening a surface of the stress relaxation layer before the step of forming the wiring. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the formed resin is an organic film. The method of manufacturing a semiconductor device according to claim 10.
A method of manufacturing a semiconductor device, wherein the organic film uses a flux whose residue changes into a thermoplastic polymer resin by a chemical reaction when heated. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the wiring is bent on the stress relaxation layer. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein a width of the wiring is larger than a width of the electrode in a connection portion between the wiring and the electrode. In the manufacturing method of the semiconductor device according to claim 1,
After forming the stress relaxation layer and forming the wiring on the stress relaxation layer, a solder part is formed on the wiring by electroless plating, and the solder part is formed into the external electrode A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
Forming the stress relaxation layer and forming a conductive layer on the stress relaxation layer;
Forming a solder portion by electroplating on the conductive layer;
Processing the conductive layer into the wiring;
Forming the solder part into the external electrode;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 14 or 15,
The method of manufacturing a semiconductor device, wherein the solder portion is formed on a base previously formed on the wiring. In the manufacturing method of the semiconductor device according to claim 14 or 15,
The method for manufacturing a semiconductor device, wherein the solder portion is formed on a solder film by plating. In the manufacturing method of the semiconductor device in any one of Claims 1-15,
A method of manufacturing a semiconductor device, comprising a step of disposing a protective member on a side surface of the wafer opposite to a surface having the electrode before cutting the wafer into individual pieces. Preparing a wafer on which electrodes are formed;
Providing a resin layer on the wafer so as to avoid at least a part of the electrode;
Forming a wiring over the top of the resin layer from the electrode,
Forming an external electrode made of solder connected to the wiring above the resin layer ;
Applying a resin to form a surface of the external electrode so as to be in contact with the wiring and including the external electrode;
A process of isotropic etching until the external electrode is exposed to the film-formed resin so that the film-formed resin remains on the wafer while avoiding the external electrode;
Cutting the wafer into individual pieces;
A method for manufacturing a semiconductor device comprising:

Images