JPH08250549A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide the semiconductor device, which can be manufactured as the high-quality product in excellent productivity even if the number of semiconductor elements becomes many, the electrodes of the semiconductor elements are made small and the electrode pitch is narrowed. CONSTITUTION: This device has the following parts. A semiconductor element 2 has a plurality of element electrodes 4, wherein integrated circuits are formed. A first insulating layer 151 is formed on the surface of the semiconductor element 2. A plurality of external electrodes 171 are formed on the first insulating layer 151. A first wiring part 161 connects the external electrode 171 and the element electrodes 4 electrically. The first conducint layers comprising these parts are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor elements are mounted on a semiconductor carrier with high density and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device mounted on a circuit board at a high density will be described with reference to FIGS.

Conventionally, when the semiconductor element 2 is mounted on the circuit board 12, as shown in FIG. 6, the semiconductor element 2 is once connected to the semiconductor carrier 3 to form the semiconductor device 1 and then mounted on the circuit board 12. Connected. There are two reasons for this.

The first reason is that if the bare semiconductor element is left as it is, it is easily scratched and cannot be inspected before mounting. Therefore,
The semiconductor element 2 is mounted on the semiconductor carrier 3 and the periphery thereof is filled and covered with an epoxy resin sealant 7 in order to allow inspection before mounting and to prevent characteristic deterioration due to humidity.

The second reason is that in the bare semiconductor element, the element electrode positions are deviated to the peripheral portion of the bare semiconductor element due to the structure, and the space is limited.
Is small and the distance between the electrodes is small. Therefore, it is difficult to directly connect the element electrode 4 to the board electrode 11 of the circuit board 12.

In order to facilitate this connection, the arrangement of the element side electrode 6 on one side is suitable for the connection to the element electrode 4 of the semiconductor element 2, and the arrangement of the substrate side electrode 8 on the opposite side is the substrate electrode of the circuit board 12. The semiconductor element 2 is connected to the one surface of the semiconductor carrier 3 suitable for connection to the semiconductor carrier 11, and the periphery thereof is filled and covered with the epoxy resin sealing agent 7 for the above reason.

Therefore, in the first conventional example, in FIG.
In the semiconductor device 1, the element electrode 4 of the semiconductor element 2 is connected to the element side electrode 6 of the semiconductor carrier 3 by providing a gold bump 5 on the element electrode 4 with cream solder or a conductive adhesive.
The gap between the connected semiconductor element 2 and the semiconductor carrier 3 and the peripheral portion of the connected semiconductor element 2 are filled and covered with an epoxy resin sealant 7. The element-side electrode 6 and the substrate-side electrode 8 are electrically connected.

When the semiconductor device 1 is connected to the circuit board 12, first, as shown in FIG. 6, bumps 9 are provided on the board-side electrodes 8 of the semiconductor carrier 3 and cream solder is applied to the board electrodes 11 of the circuit board 12. Print 13.

Next, as shown in FIG. 7, the semiconductor device 1
The board-side electrode 8 is positioned and placed on the board electrode 11 of the circuit board 12, and is heated to melt and cure the applied cream solder 13, so that the board-side electrode 8 is
Connect to.

Next, a second conventional example will be described with reference to FIG.

In FIG. 8, the semiconductor device 1 has gold bumps 5 formed on a plurality of element electrodes 4 of a semiconductor element 2,
The gold bump 5 is connected to the element side electrode 6 formed on the polyimide film 14 by the conductive adhesive 5a,
A gap 7 between the semiconductor element 2 and the polyimide film 14 is filled with an epoxy resin sealant 7. Then, bumps 9 are provided on the element-side electrodes 6 and are connected to the electrodes on the circuit board. Although FIG. 8 shows a cross section, in reality,
A large number of device electrodes 4 which are biased to the peripheral portion of the semiconductor device 2 are densely arranged in the direction perpendicular to the plane of the drawing.
Are arranged in a lattice shape in a wide space in the center of the semiconductor element 2.

[0012]

However, in the structure of the above conventional example, as shown in FIG. 5, the steps from the semiconductor element wafer to the shipment as a semiconductor device are divided into semiconductor element wafers in a dividing step. Divide into individual semiconductor elements, repeat bump formation for each semiconductor element by the number of element electrodes in the bump forming process, and complete the bump formation in the positioning / joining process. , It is necessary to position and bond to the semiconductor carrier one by one.

Therefore, when the number of device electrodes of a semiconductor device increases as in recent years, there is a problem that the production process takes a very long time.

There is also a problem that the curing process of the sealing agent 7 shown in FIGS. 6 and 7 also requires a long time.

As characteristics required for the semiconductor carrier 3, the flatness is such that the amount of warpage is 10 μm or less and the size of the substrate-side electrode is 100 μm × 100 μm or more in order to maintain the reliability of the electrode bonding strength. , The amount of warpage is 10 μm
If it exceeds the range, electrode bonding failure occurs, and if the area of the substrate-side electrodes becomes insufficient or the pitch becomes too narrow, high-quality manufacturing becomes difficult and problems such as bridges occur.

The present invention solves the above problems and increases the number of device electrodes of a semiconductor device, reduces the device electrode of a semiconductor device, and narrows the electrode pitch, thereby producing a high-quality product with high productivity. An object of the present invention is to provide a semiconductor device that can be manufactured and a manufacturing method thereof.

[0017]

In order to solve the above-mentioned problems, a semiconductor device according to the first invention of the present application is provided with a semiconductor element having an integrated circuit and having a plurality of element electrodes, and formed on the surface of the semiconductor element. A first insulating layer, a plurality of external electrodes formed on the first insulating layer, and a first wiring electrically connecting the external electrode and the element electrode
And a conductive layer.

In order to solve the above problems, the semiconductor device of the second invention of the present application includes a semiconductor element having an integrated circuit and a plurality of element electrodes, and a first insulating layer formed on the surface of the semiconductor element. A first conductive layer formed on the first insulating layer, the first conductive layer including a first wiring electrically connected to the device electrode; a second insulating layer formed on the first conductive layer; A second conductive layer including a plurality of external electrodes formed on the second insulating layer and a second wiring electrically connecting the external electrodes to the first wiring or the element electrode. Characterize.

In order to solve the above-mentioned problems, the semiconductor device of the second invention of the present application has a multilayer wiring structure in which an insulating layer and a conductive layer are repeatedly formed on the surface of a semiconductor element. It is preferable that an outer electrode electrically connected to the element electrode of the semiconductor element through the outermost surface is formed on the outermost surface.

In the semiconductor device of the first, second or third invention of the present application, in order to solve the above problems, the thermal expansion coefficient of the insulating material of the insulating layer is determined by the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the circuit board. It is preferable that the value is an intermediate value with respect to the coefficient of thermal expansion.

In the semiconductor device of the first, second, third or fourth invention of the present application, in order to solve the above problems, it is preferable that the insulating material of the insulating layer is a photosensitive epoxy resin. .

A method of manufacturing a semiconductor device according to the third invention of the present application is
In order to solve the above-mentioned problems, an insulating layer made of a photosensitive insulating material is formed on the surface of a semiconductor element having an integrated circuit and a plurality of element electrodes, exposed using a mask, and developed to develop the element. A first insulating layer forming step of providing a first insulating layer having a through hole for the electrode; forming a conductive layer of a conductive material on the first insulating layer and shaping the plurality of external electrodes; And a first conductive layer forming step of providing a first conductive layer consisting of a first wiring electrically connecting the element electrode with each other.

A method of manufacturing a semiconductor device according to the fourth invention of the present application is
In order to solve the above-mentioned problems, an insulating layer made of a photosensitive insulating material is formed on the surface of a semiconductor element having an integrated circuit and a plurality of element electrodes, exposed using a mask, and developed to develop the element. A first insulating layer forming step of providing a first insulating layer having a through hole for an electrode, and a first wiring for forming a conductive layer of a conductive material on the first insulating layer, shaping the conductive layer, and connecting to the element electrode First providing a first conductive layer having
Conductive layer forming step, and a second insulating layer having a through hole for the first wiring formed by forming an insulating layer of a photosensitive insulating material on the first conductive layer, exposing using a mask, and developing. And forming a conductive layer of a conductive material on the second insulating layer and shaping the conductive layer to form a plurality of external electrodes, and the external electrodes and the first wirings or the element electrodes. A second conductive layer including a second wiring electrically connecting the second conductive layer and the second conductive layer forming step.

In order to solve the above-mentioned problems, the semiconductor device manufacturing method according to the fourth invention of the present application provides the multilayer wiring structure on the surface of the semiconductor element by repeating the insulating layer forming step and the conductive layer forming step. It is preferable to provide an external electrode on the outermost surface that is electrically connected to the device electrode of the semiconductor device via the multilayer wiring structure.

In order to solve the above problems, the semiconductor device manufacturing method according to the third or fourth aspect of the present invention includes an insulating layer forming step and a conductive layer forming step for a plurality of semiconductor elements in a wafer state. It is preferable to apply.

[0026]

According to the semiconductor device of the present invention and the method of manufacturing the semiconductor device of the present invention, an insulating layer made of a photosensitive insulating material is formed on the surface of a semiconductor element having an integrated circuit and a plurality of element electrodes, and a mask is used. Exposing using, developing and forming a first insulating layer having a first insulating layer having a through hole for the device electrode; and forming a conductive layer of a conductive material on the first insulating layer, This is due to the combination with the first conductive layer forming step of forming the first conductive layer having the first wiring that is shaped and connected to the element electrode, and since these steps can utilize the results of the manufacturing technology of the semiconductor element, It is possible to obtain a high-quality semiconductor device corresponding to the element electrodes of the semiconductor element to be miniaturized and the pitch thereof.

Further, the time-consuming prior art process of mounting a bump on each element electrode of the semiconductor element is eliminated, and the element electrode and the external electrode are collectively attached to each semiconductor element and further to each wafer. Since the electrodes are joined together, the productivity can be greatly improved.

Further, by using an insulating material having a coefficient of thermal expansion intermediate between the coefficient of thermal expansion of the semiconductor element and the coefficient of thermal expansion of the circuit board as the insulating material to be used, the thermal stress caused by the difference in thermal expansion is generated. Can be alleviated and reliability can be improved.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the semiconductor device of the present invention will be described with reference to FIGS.

1 and 2, the structure of the semiconductor device 1 according to the present embodiment has a semiconductor element 2 having a plurality of element electrodes 4.
A first insulating layer 151 is formed on the top of the device electrode 4, and a through hole 4 a is provided on the device electrode 4. First insulating layer 15
A first wiring 161 and a first external electrode 171 are provided on the first wiring 1, and the first wiring 161 connects the first external electrode 171 and the device electrode 4. First insulating layer 151 and first wiring 1
The second insulating layer 15 is formed on the first electrode 61 and the first outer electrode 171.
2 is provided, and the through hole 17 is provided on the first external electrode 171.
1a is opened. The first external electrode 171 becomes the external electrode of the semiconductor device 1 of this embodiment.

As shown in FIG. 2, the element electrodes 4 are arranged in the peripheral portion of the semiconductor element 2 in a biased manner depending on the structure of the semiconductor element 2, so that the semiconductor element 2 is downsized and the element is reduced. When the number of electrodes 4 increases, the device electrodes 4
Area becomes smaller and the pitch between electrodes becomes narrower.
The external electrode 171 is arranged in a wide space in the central portion of the semiconductor element 2 and has few restrictions on the shape, area, and arrangement, and as shown in FIG. 2, the external electrode 171 can be easily connected to the substrate electrode of the circuit board.
For example, the layout can be freely designed in a grid pattern or the like.

A second embodiment of the semiconductor device of the present invention will be described with reference to FIG.

In FIG. 3, the semiconductor device 1a of this embodiment is shown.
The structure of is a multilayer structure of the structure of the first embodiment.

A first insulating layer 151 is formed on the semiconductor element 2 having a plurality of element electrodes 4, and a through hole 4a is provided on the element electrode 4.

A first wiring 161 is formed on the first insulating layer 151.
And the first connection electrode 161a are provided, and the first wiring 161
Is connected to the element electrode 4 and the first connection electrode 161a.

The first insulating layer 151, the first wiring 161, and the first
The second insulating layer 152 is provided on the connection electrode 161a, and the through hole 161b is provided on the first connection electrode 161a.

A second wiring 162 is formed on the second insulating layer 152.
And a second external electrode 172 are provided, and the second wiring 162 is connected to the first connection electrode 161a.

The second insulating layer 152, the second wiring 162, and the second
A third insulating layer 153 is provided on the external electrode 172, and a through hole 172a is provided on the second external electrode 172.

The above-mentioned multi-layer structure is not limited to two layers and can be any number of layers, and circuit elements such as resistors and capacitors can be added to the wiring portions of these layers.

A method of manufacturing the semiconductor device of the present invention will be described with reference to FIGS.

In FIG. 4, first, in the first insulating layer forming step, the first insulating layer 151a is formed of a photosensitive insulating material on the surface of the semiconductor element 2 having the element electrode 4. The photosensitive insulating material is preferably an epoxy resin. The first insulating layer 151a may be formed by printing a liquid material or by attaching a film-shaped material.

Next, in the exposure step, exposure 18 is performed using a mask 17 formed so that light of a predetermined pattern will pass.
To do.

Next, in the developing step, by developing, a through hole 4a is provided on the device electrode 4, and the first insulating layer 1 is formed.
51 is formed.

Next, in the first conductive material layer forming step, the first conductive material layer 171c is formed on the first insulating layer 151, the through hole 4a and the device electrode 4. This first
For forming the conductive material layer 171c, various processing methods such as plating, sputtering and vapor deposition can be freely selected as long as a thin film can be formed and a fine pattern can be formed.

Next, in a shaping step, etching is performed from the first conductive material layer 171c, leaving a necessary portion, to form a first wiring 161 and an external electrode 171. Of course, the shaping method can be freely selected.

Next, in the second insulating layer forming step, the second insulating layer 152a is formed of a photosensitive insulating material on the surfaces of the first insulating layer 151, the first wiring 161, and the external electrode 171. The photosensitive insulating material is preferably an epoxy resin.
The second insulating layer 151a may be formed by printing a liquid material or by attaching a film-shaped material.

Next, in the exposure / development process, the through hole 171a is formed on the external electrode 171 by exposing and developing.
And the second insulating layer 152 is formed.

In FIG. 4, the plurality of external electrodes 171 appear to have a small mutual spacing, but in reality, as shown in FIG. Is.

In some cases, the n-th wiring layer forming step and the n-th insulating layer forming step are repeated to form a multilayer structure. At that time, elements such as resistors and capacitors can be added to each wiring layer.
As shown in Table 1, the insulating material used above is preferably a material having a thermal expansion coefficient intermediate between the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the circuit board.

[0050]

[Table 1]

Although FIG. 4 used in the description of the embodiment is such that the wiring layer forming step and the insulating layer forming step are performed after the semiconductor element wafer is divided, the nth wiring layer forming step is performed. In the step and the n-th insulating layer forming step, the semiconductor elements of the entire wafer can be collectively processed in the state before the division of the semiconductor element wafer, so that the working efficiency is significantly improved.

Further, since the wiring layer forming step and the insulating layer forming step are the same steps as those of the semiconductor element manufacturing step, the processing accuracy thereof can be the same as that of the semiconductor element manufacturing record. Therefore, it is possible to manufacture high-quality semiconductor devices corresponding to the ultra-miniaturized electrodes and the pitch thereof.

Based on FIG. 5, the process of the present invention and the process of the conventional example will be compared.

In FIG. 5, the conventional example on the right side is as described above, but in the case of the present invention on the left side, the nth wiring layer forming step and the nth insulating layer forming step are performed on the semiconductor element wafer. In the state before the division, since the semiconductor elements of the entire wafer can be collectively processed, in the conventional example, after dividing the semiconductor element wafer, for each one of the semiconductor elements, for each of those electrodes, The work efficiency is significantly improved as compared with forming bumps.

[0055]

In the semiconductor device and the manufacturing method thereof according to the present invention, since the wiring layer forming step and the insulating layer forming step are both the same steps as those of the semiconductor element manufacturing step, the semiconductor is miniaturized. The electrode of the element and the pitch thereof can be dealt with, and an effect that a high quality semiconductor device can be manufactured is obtained.

Further, in the present invention, the time-consuming prior art process of attaching bumps to each electrode of the semiconductor element is eliminated, and the electrode indirect connection is performed collectively for each semiconductor element and further for each wafer. Therefore, there is an effect that the productivity can be remarkably improved.

Also, by using an insulating material having a coefficient of thermal expansion intermediate between the coefficient of thermal expansion of the semiconductor element and the coefficient of thermal expansion of the circuit board, the thermal stress generated by the difference in thermal expansion is used. This has the effect of alleviating the above and improving the reliability.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a configuration of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a configuration of a first embodiment of a semiconductor device of the present invention.

FIG. 3 is a side sectional view showing the configuration of a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a process drawing showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a diagram comparing processes of the present invention and a conventional example.

FIG. 6 is a side sectional view showing a configuration and a method of using a semiconductor device of a first conventional example.

FIG. 7 is a side sectional view showing the configuration and usage of a semiconductor device of a first conventional example.

FIG. 8 is a side sectional view showing a configuration of a semiconductor device of a second conventional example.

[Explanation of symbols]

 1 Semiconductor Device 1a Semiconductor Device 2 Semiconductor Element 4 Element Electrode 4a Through Hole 17 Mask 18 Exposure 151 First Insulating Layer 151a First Insulating Layer 152 Second Insulating Layer 152a Second Insulating Layer 153 Third Insulating Layer 161 First Wiring 161a First connection electrode 161b Through hole 162 Second wiring 171 External electrode 171a Through hole

Claims (9)

[Claims] 1. A semiconductor device having an integrated circuit and having a plurality of device electrodes, a first insulating layer formed on a surface of the semiconductor device, and a plurality of external electrodes formed on the first insulating layer. And a first conductive layer including a first wiring that electrically connects the external electrode and the element electrode. 2. A semiconductor element having an integrated circuit and having a plurality of element electrodes, a first insulating layer formed on a surface of the semiconductor element, and an element electrode electrically formed on the first insulating layer. A first conductive layer composed of electrically connected first wirings, a second insulating layer formed on the first conductive layer, and a plurality of external electrodes formed on the second insulating layer, A semiconductor device comprising: a second conductive layer including a second wiring electrically connecting the external electrode and the first wiring or the element electrode. 3. An external electrode having a multilayer wiring structure in which an insulating layer and a conductive layer are repeatedly formed on the surface of a semiconductor element, and electrically connected to an element electrode of the semiconductor element through the multilayer wiring structure. The semiconductor device according to claim 2, wherein is formed on the outermost surface. 4. The semiconductor device according to claim 1, 2 or 3, wherein the thermal expansion coefficient of the insulating material of the insulating layer is an intermediate value between the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the circuit board. 5. The semiconductor device according to claim 1, wherein the insulating material of the insulating layer is a photosensitive epoxy resin. 6. A through hole for the device electrode, wherein an insulating layer made of a photosensitive insulating material is formed on the surface of a semiconductor device having an integrated circuit and having a plurality of device electrodes, exposed using a mask and developed. A first insulating layer forming step of providing a first insulating layer having: and forming a conductive layer of a conductive material on the first insulating layer and shaping the conductive layer to form a plurality of external electrodes, the external electrodes and the element electrodes. And a first conductive layer formed of a first wiring electrically connecting the first conductive layer and the first conductive layer. 7. A through hole for the device electrode, wherein an insulating layer made of a photosensitive insulating material is formed on the surface of a semiconductor device having an integrated circuit and having a plurality of device electrodes, exposed using a mask and developed. A first insulating layer forming step of providing a first insulating layer having: and a first wiring having a first wiring for forming a conductive layer made of a conductive material on the first insulating layer, shaping the conductive layer, and connecting to the element electrode. A step of forming a first conductive layer, a step of forming a conductive layer, forming an insulating layer of a photosensitive insulating material on the first conductive layer, exposing using a mask, and developing to form a through hole for the first wiring. A second insulating layer having a second
An insulating layer forming step, and forming a conductive layer made of a conductive material on the second insulating layer and shaping the conductive layer to electrically connect the plurality of external electrodes to the external electrodes and the first wiring or the element electrode. A second conductive layer including a second wiring to be connected is provided.
And a step of forming a conductive layer. 8. An insulating layer forming step and a conductive layer forming step are repeated on a surface of a semiconductor element to provide a multilayer wiring structure, and the layer is electrically connected to an element electrode of the semiconductor element through the multilayer wiring structure. The method for manufacturing a semiconductor device according to claim 7, wherein the electrode is provided on the outermost surface. 9. A plurality of semiconductor elements in a wafer state,
The insulating layer forming step and the conductive layer forming step are performed.
Or the method for manufacturing a semiconductor device according to 8.