JP3482121B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element such as a transistor, and more particularly to a semiconductor device which enables high-density mounting.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, semiconductor devices have been required to have smaller size, higher density, and higher speed. Therefore, for example, LOC (lead-on-chip) and SON (small outline non-lead) are used as memory packages.
, Etc., or μBG using TAB tape
A (micro ball grid array)
6-504408) has been developed.

A conventional semiconductor device called a μBGA will be described below with reference to FIG. Figure 4 (a)
Is a perspective view of a conventional semiconductor device called μBGA, FIG.
4B is a sectional view taken along line IV-IV showing the state before the metal balls are formed in FIG. Figure 4
In (a) and (b), 101 is a semiconductor chip containing a semiconductor element such as a transistor, 102 is a wiring circuit sheet provided on the semiconductor chip 101, and 103 is between the semiconductor chip 101 and the wiring circuit sheet 102. An intervening flexible low elastic modulus material film, 104 is a partial lead included in the wiring circuit sheet 102, and 105 is the semiconductor chip 10.
1 is an electrode, 106 is a land of the wiring circuit sheet 102, and 107 is a metal ball provided on the land 106 for connecting the semiconductor device to the outside.

As shown in FIGS. 4 (a) and 4 (b), μBG
A semiconductor device referred to as A has a structure in which a wiring circuit sheet 102 is bonded onto a semiconductor chip 101 via a low elastic modulus material film 103, and an electrode 105 of the semiconductor chip 101.
And the land 106 of the wiring circuit sheet 102 are electrically connected to each other through the partial lead 104, and the metal ball 107 is provided on the land 106.

[0005]

However, according to the above-described conventional semiconductor device, since there is a restriction on the partial lead 104 in order to reduce the size, the partial portion is formed near the corner of the wiring circuit sheet 102 in plan view. There was a non-wiring region where the lead 104 could not be wired.

Hereinafter, the non-wiring region will be described with reference to FIG. FIG. 5 is a plan view showing the vicinity of a corner of a conventional semiconductor device. In FIG. 5, in order to reduce the size of the semiconductor device, the partial lead 104 has a portion extending from the outer edge of the wiring circuit sheet 102 that has a minimum length required for bending and connection and is orthogonal to the outer edge. Is formed. Therefore, the wiring circuit sheet 102
In the corner portion of the above, that is, in the vicinity of the corner portion of the semiconductor chip 101, the interval between the partial leads 104 is narrowed, so that the non-wiring region 108 in which wiring cannot be performed occurs.
Further, since the partial lead 104 is not provided in the non-wiring region 108, the degree of freedom in wiring design is lowered and high-density mounting is hindered.

In order to solve the conventional problems described above, the present invention provides a semiconductor device in which the degree of freedom in wiring design is improved and wiring is possible at high density by enabling wiring even in the vicinity of the corners of a semiconductor chip. The purpose is to provide.

[0008]

The semiconductor device of the present invention comprises:
As described in claim 1, a semiconductor chip having an electrode on the main surface, and an opening provided on the main surface and above the electrode.
Of the passivation film having a
Low elastic modulus on top, with electrodes located outside
A layer, one end connected to the electrode and the other end low bullet
With the metal wiring provided on the property rate layer ,
A chamfered portion, which is chamfered when the corner portion is viewed in a plan view, is provided at a corner portion of the low elastic modulus layer when viewed in a plan view, and the metal wiring extends across the chamfered portion.

Thus, a chamfered portion, which is chamfered when the corner is seen in a plan view, is provided at a corner of the low elastic modulus layer in a plan view, and the metal wiring extends so as to cross the chamfered section. Therefore, wiring is possible even for the electrodes provided at the corners of the semiconductor chip, and the degree of freedom of wiring and the packaging density are improved. Furthermore, since the distance between the metal wiring provided in the chamfered portion and the center of the semiconductor device is shortened, the thermal stress when a thermal cycle is applied is reduced, resulting in low elasticity.
The peeling of the metal wiring from the index layer is suppressed. In claim 2
As described, the semiconductor device according to claim 1
The low elastic modulus film must be made of a polymer with insulating properties.
Is preferred.

As described in claim 3 or 4 ,
In the semiconductor device according to claim 1, it is preferable that the chamfered portion draw a straight line or an arc when seen in a plan view.

[0011] This ensures that the metallic wires, since it is provided so as to traverse to ensure chamfered portion formed so as to draw a straight line or an arc in plan view, electrodes provided at a corner of the semiconductor chip Also, the metal wiring is surely wired.

As described in claim 5 ,
In the semiconductor device of 3 or 4 , the external terminal is formed by extending a part of the metal wiring on the low elastic modulus layer , and the insulating material is formed by opening the external terminal and has a property of repelling a conductive material. And a protective film.

Thus, when the external terminals of the semiconductor device and the terminals of the external device are connected using the conductive material, the metal wiring other than the external terminals and the electrodes of the semiconductor chip are surely protected from the conductive material. be able to.

Claims, as set forth in claim 6 ,
The semiconductor device of 5 may further include a protruding electrode provided on the external terminal.

Thus, the external terminal of the semiconductor device and the terminal of the external device can be reliably connected via the protruding electrode.

As described in claim 7 , in the semiconductor device according to claim 1, it is preferable that the peripheral edge portion of the low elastic modulus layer is inclined.

Thus, the metal wiring is stably formed by being provided on the inclined surface at the peripheral portion of the low elastic modulus layer having the inclined cross-sectional shape.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a perspective view showing an outline of a semiconductor device according to the present invention with a part of a solder resist opened. In FIG. 1, reference numeral 10 denotes a semiconductor chip containing a semiconductor element such as a transistor, and 20
Is an insulating layer provided on the semiconductor chip 10 and has a low elastic modulus layer having an inclined surface at its outer edge portion, and 21A is a low elastic modulus layer 20.
Chamfered portions that are linearly chamfered at the respective corners viewed in a plane, 30 is a pad provided on an electrode (not shown) of the semiconductor chip 10, 31 is an outer edge of the low elastic modulus layer 20 from the pad 30. Wiring patterns that are orthogonal to each other and extend inside the semiconductor device, 32 is a land provided on the low elastic modulus layer 20 and connected to the pad 30 via the wiring pattern 31, and 40 is a solder resist formed so as to cover portions other than the land 32. , 50 are metal balls provided on the land 32 for connecting the semiconductor device and the outside. The pad 30, the wiring pattern 31, and the land 32 together form a metal wiring 33.

Here, the semiconductor device according to the present invention is characterized in that each corner of the low elastic modulus layer 20 in plan view has a chamfered portion 21A which is linearly chamfered in plan view. The wiring pattern 31 that passes through the chamfered portion 21A is orthogonal to the outer edge of each chamfered portion 21A of the low elastic modulus layer 20.

Details of the vicinity of each corner in the semiconductor device according to the present invention will be described with reference to FIG. Figure 2 (a)
2A and 2B are plan views showing details in the vicinity of corners of the semiconductor device shown in FIG. 1 and FIG. 2B, respectively, of a modification of the semiconductor device shown in FIG.

As shown in FIG. 2A, a wiring pattern 31 is formed at a predetermined interval perpendicular to the outer edge of each chamfered portion 21A of the low elastic modulus layer 20. This makes it possible to use the region of the chamfered portion 21A near each corner, and the degree of freedom in wiring design is improved.

Further, from the electrodes 11 provided in the vicinity of each corner of the semiconductor chip 10 to the land on the low elastic modulus layer 20 (see FIG. 1).
Since the number of lands can be increased by providing the wiring pattern 31 on the land 32), the packaging density is improved.

A modified example of the semiconductor device according to the present invention will be described with reference to FIG. As shown in FIG. 2B, a chamfered portion 21B chamfered in an arc shape in a plan view can be provided at each corner of the low elastic modulus layer 20 in a plan view. Also in this case, the wiring pattern 31 that passes through the chamfered portion 21B is substantially orthogonal to the outer edge of each chamfered portion 21B of the low elastic modulus layer 20. Therefore, each chamfered portion 21 having no corners
Since the entire arc-shaped region can be used in B, the degree of freedom in wiring design is further improved, and the land on the low elastic modulus layer 20 from the electrode 11 near each corner of the semiconductor chip 10 (land 32 in FIG. 1). By providing the wiring pattern 31 in (1), the number of lands can be increased, so that the mounting density is improved.

As shown in FIG. 2A, the low elastic modulus layer 2
Regarding the wiring rule, that is, the wiring that can be formed is the case where the outer edge is chamfered linearly at each corner of 0 and the conventional case where each corner is a right angle as shown in FIG. The width and the wiring interval were compared. In the case of the conventional semiconductor device shown in FIG. 5A, at each corner,
A wiring rule having a wiring width of 20 μm and a wiring interval of 40 μm was required. On the other hand, in the case of the semiconductor device according to the present invention shown in FIG. 2A, wiring can be performed at each corner with a wiring rule of a wiring width of 40 μm and a wiring interval of 40 μm.

As described above, according to the present invention, the degree of freedom in wiring design is improved and the number of wiring patterns is increased when the same wiring width is used, as compared with the conventional semiconductor device. Since the number can be increased, a semiconductor device having an improved packaging density can be realized.

Further, when the number of wiring patterns is the same, the wiring width can be widened, so that a highly reliable semiconductor device can be realized.

Further, in any of the semiconductor devices shown in FIGS. 2A and 2B, a portion farthest from the center, that is, the wiring pattern 31 at each corner of the low elastic modulus layer 20 and the center of the semiconductor device. The distance is shortened. This allows
When a thermal cycle is applied, the low elastic modulus layer 20
The thermal stress caused by the difference in thermal expansion coefficient between the wiring pattern 31 and the wiring pattern 31 is reduced. Therefore, peeling of the wiring pattern 31 from the low elastic modulus layer 20 is suppressed, and a semiconductor element having high reliability with respect to the application of the heat cycle is realized.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. Fig.3 (a)-
3E is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 1.

First, as shown in FIG. 3A, on the electrode 11 and the passivation film 12 formed on the main surface of the semiconductor chip 10, an insulator having photosensitivity and a low elastic modulus is formed. The resin is applied and then dried to form the resin film 15. The material having photosensitivity for forming the resin film 15 may be a polymer having a low elastic modulus and an insulating property such as polyimide and epoxy.

Next, as shown in FIG. 3B, the resin film 1
5 is sequentially exposed and developed to form the low elastic modulus layer 20 in which the electrode 11 is opened. In this case,
In the low elastic modulus layer 20, the low elastic modulus layer 20 is formed such that each corner is chamfered in a straight line shape or an arc shape in a plan view. In addition, for example, scattered light instead of parallel light is used in the exposure, and the cross-sectional shape of the low elastic modulus layer 20 in the opening is formed in a tapered shape instead of perpendicular to the electrode 11.

Next, as shown in FIG. 3C, a metal thin film layer made of, for example, Ti / Cu is formed on the entire main surface of the semiconductor chip 10 by a vacuum deposition method, a sputtering method, a CVD method or an electroless plating method. After forming, the metal thin film layer is patterned. As a result, the predetermined metal wiring 3 including the pad 30, the wiring pattern 31, and the land 32 is formed on the main surface of the semiconductor chip 10.
3 is formed. The pattern of the metal wiring 33 is the pad 30.
, The number of pins, and the area of the semiconductor chip 10 are taken into consideration.

The patterning is performed as follows.
A photosensitive resist is applied on the metal thin film layer, the resist other than a predetermined pattern portion is cured by exposure, and then the resist in the pattern portion is removed. A metal layer having a large film thickness made of, for example, Cu is formed on the pattern portion using electrolytic plating, and then the resist is melted and removed. Then, it is immersed in an etching solution to dissolve the metal thin film layer and leave a metal layer having a large film thickness to form a predetermined metal wiring.

A metal film is deposited on the entire surface, a photoresist is applied on the metal film, an etching mask resist is formed on a predetermined pattern portion by using a photolithography technique, and the resist is used as a mask. Alternatively, the metal wiring may be formed by etching the metal layer.

Next, as shown in FIG. 3D, after applying a photosensitive solder resist on the low elastic modulus layer 20,
A photolithography technique is used to form the solder resist 40 so that only the land 32 is exposed. The solder resist 40 protects the pad 30 and the wiring pattern 31, which are portions of the metal wiring other than the land 32, from the solder melted in the subsequent process.

Next, as shown in FIG. 3 (e), solder,
A metal ball 50 made of copper, nickel or the like, or made of a solder-plated metal is placed on the land 32,
The metal ball 50 and the land 32 are fusion-bonded. Through the above steps, the semiconductor device according to the present invention can be obtained.

According to the method of manufacturing a semiconductor device of this embodiment, the low elastic modulus layer 20 is formed such that each corner is chamfered in a straight line shape or a circular arc shape in plan view. Therefore, the semiconductor device according to the present invention can be easily manufactured.

In the above description, the cross-sectional shape of the low elastic modulus layer 20 in the opening is tapered.
Instead, it may have an arc shape, and the cross section may be perpendicular to the main surface of the semiconductor chip.

Further, the low elastic modulus layer 20 is formed by exposure and development.
However, instead of this, the low elastic modulus layer 20 in which each corner is chamfered in a straight line shape or an arc shape in a plan view may be formed by using, for example, a screen printing method.

Further, in order to form the resin film 15, a resin made of an insulating material having photosensitivity and a low elastic modulus was applied. Not limited to this, a photosensitive insulating material formed in advance in a film shape may be used. In this case, the film-shaped insulating material is bonded onto the semiconductor chip 10 and then exposed and developed to form the semiconductor chip 10.
The electrode 11 of is exposed.

Further, an insulating material having no photosensitivity can also be used. In this case, the electrode 11 of the semiconductor chip 10 is exposed by mechanical processing such as laser or plasma, or chemical processing such as etching.

[0041]

According to the present invention, the metal wiring has a low elastic modulus.
Since it is provided so as to cross the chamfered portion of the layer , wiring is possible even for the electrodes provided at the corners of the semiconductor chip, and a semiconductor device with improved wiring freedom and packaging density is realized. It

Further, since the distance between the metal wiring provided in the chamfered portion and the center of the semiconductor device is shortened, the thermal stress when a thermal cycle is applied is reduced. Therefore, peeling of the metal wiring from the insulating layer is suppressed,
A semiconductor device having high reliability with respect to thermal cycles is realized.

Further, the metal wiring is stably formed by being provided on the inclined surface at the peripheral portion of the low elastic modulus layer having the inclined cross-sectional shape.

[Brief description of drawings]

FIG. 1 is a perspective view showing an outline of a semiconductor device according to the present invention with a part of a solder resist opened.

FIG. 2A is a view of the semiconductor device shown in FIG.
2A and 2B are plan views showing details in the vicinity of respective corners of the modification of the semiconductor device shown in FIG.

3A to 3E are cross-sectional views showing manufacturing steps of the semiconductor device shown in FIG.

4A is a perspective view of a conventional semiconductor device called μBGA, and FIG. 4B is a cross-sectional view taken along line IV-IV showing a state before metal balls are formed in FIG.

5 is a plan view showing the vicinity of a corner of the conventional semiconductor device shown in FIG.

[Explanation of symbols] 10 semiconductor chips 11 electrodes 12 passivation film 15 Resin film 20 Low elastic modulus layer (insulating layer) 21A, 21B Chamfer 30 pads 31 wiring pattern 32 lands (external terminal) 33 Metal wiring 40 Solder resist (protective film) 50 metal balls (protruding electrodes)

Front page continuation (72) Inventor Takahiro Kumakawa 1-1 Sachimachi, Takatsuki, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (56) References JP-A-9-306945 (JP, A) JP-A-8-203906 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 23/12 H01L 21/3205

Claims (7)

(57) [Claims] 1. A semiconductor chip having an electrode on the main surface, and an opening provided on the main surface and above the electrode.
A passivation film, and the electrode is located outside the passivation film.
A low elastic modulus layer that is provided so as to, be connected to the the one end electrode, is low the other end
Provided with a metal wiring and provided on the elastic modulus layer, the which chamfers the corner portion is chamfered in plan view the corner portion planarly viewed low modulus layer is provided, wherein A semiconductor device, wherein the metal wiring extends so as to cross the chamfered portion. 2. The semiconductor device according to claim 1, wherein the low elastic modulus film is made of a polymer having an insulating property.
A semiconductor device characterized by: 3. The semiconductor device according to claim 1, wherein the chamfered portion draws a straight line when seen in a plan view. 4. The semiconductor device according to claim 1, wherein the chamfered portion draws an arc when viewed two-dimensionally. 5. The semiconductor device according to claim 3 or 4 , wherein an external terminal is provided on the low elastic modulus layer so that a part of the metal wiring extends, and the external terminal is provided by opening the conductive terminal. A semiconductor device further comprising a protective film made of an insulating substance having a property of repelling a material. 6. The semiconductor device according to claim 5 , further comprising a protruding electrode provided on the external terminal. 7. The semiconductor device according to claim 1, wherein a peripheral portion of the low elastic modulus layer is inclined.